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公开(公告)号：FR2623651A1
公开(公告)日：1989-05-26
申请号：FR8716063
申请日：1987-11-20
Inventor： DEVIN JEAN , JEAN DEVIN LAURENT SOURGEN ET GILLE , GILLE , SOURGEN LAURENT
IPC: G11C11/00 , G11C16/04 , G11C14/00 , G11C16/06 , G11C16/10 , G11C17/00 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
Abstract: Pour éviter une différenciation technologique entre des cellules mémoires vives et des cellules mémoires mortes d'un même plan mémoire on réalise toutes les cellules mémoires en une même technologie. Ces cellules mémoires sont alors composées essentiellement de transistors à grille flottante. La programmation des cellules mémoires vives se fait, classiquement, par injection ou non de charges électroniques dans les grilles flottantes des transistors. La programmation IM, Im ou non des cellules mémoires mortes se fait par implantation d'impuretés DELTAI dans les canaux de conduction des transistors à grille flottante de ces cellules mémoires. On montre qu'on améliore la dissimulation du contenu destiné à rester cacher des cellules mémoires mortes, tout en améliorant les conditions de réalisation de prototypes à la demande.
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公开(公告)号：FR2690748A1
公开(公告)日：1993-11-05
申请号：FR9205425
申请日：1992-04-30
Inventor： PIERRE FOURNEL RICHARD , FOURNEL RICHARD PIERRE , LAURENT SOURGEN , SOURGEN LAURENT
IPC: G06F1/28 , H03K17/22 , G01R19/165
Abstract: On propose un circuit qui comporte deux capacités (C1, C2), et un ensemble d'interrupteurs (K1, K2, K3) actionnés périodiquement et agencés pour: - dans une première phase (H) appliquer aux bornes de la première capacité (C1) la tension d'entrée et appliquer à la grille d'un transistor de détection (T1) la tension de la deuxième capacité (C2), les deux capacités étant isolées l'une de l'autre, - dans une deuxième phase relier les deux capacités pour charger la deuxième par la première, les capacités étant isolées de l'entrée (E) et de la grille du transistor de détection, le circuit comportant encore un moyen (T2) pour précharger le drain du transistor de détection (T1) pendant la première phase, un moyen (R) pour décharger la deuxième capacité pendant la première phase (H), et un circuit de verrouillage (I, T3) du niveau logique du drain du transistor de détection.
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公开(公告)号：FR2748616A1
公开(公告)日：1997-11-14
申请号：FR9605719
申请日：1996-05-07
Applicant: SGS THOMSON MICROELECTRONICS
Inventor： LISART MATHIEU , SOURGEN LAURENT
Abstract: The circuit comprises a voltage booster which produces a high DC output. A control circuit uses this to generate a ramped programming voltage. The source of a first P-type load transistor is connected to the output of the voltage booster. Its drain is coupled to a capacitor and by its gate to the control circuit. The high voltage programming output is produced at the transistor drain. The control circuit includes a pulse generator which applies a stepped voltage to the load transistor gate. The capacitor is formed by line of bits in a memory map. The control circuit also comprises a P-type transistor which is mounted in diode configuration and is used to charge the capacitor with a constant current.
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公开(公告)号：FR2678094B1
公开(公告)日：1993-10-08
申请号：FR9108126
申请日：1991-06-20
Applicant: FRANCE TELECOM , POSTE , SGS THOMSON MICROELECTRONICS SA
Inventor： DEPRET ERIC , SOURGEN LAURENT
IPC: G11C17/00 , G06F12/16 , G06K19/07 , G07F7/08 , G07F7/10 , G11C16/02 , G11C16/10 , H03K21/00 , G06K19/073
Abstract: The invention relates to a passive memory card integrated circuit for counting units comprising p data counting memory stages (10, 11, 12) containing numbers of respective boxes n1...np, writing being carried out into a box of an upper stage each time all the boxes of a lower stage have been validated, the boxes of the lower stages then being erased. This circuit comprises p-1 indicator stages (21, 22) which are identical to the p-1 stages of higher rank of the p counting stages, the addressing logic of the indicator stages being such that the boxes of these indicator stages are simultaneously write-addressed with the boxes of the corresponding counting stages and, after writing, are addressed for erasing, at the same time as the boxes of the stages lower than that which has just been validated. … …
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公开(公告)号：DE3875431D1
公开(公告)日：1992-11-26
申请号：DE3875431
申请日：1988-08-26
Applicant: SGS THOMSON MICROELECTRONICS
Inventor： FRUHAUF SERGE , SOURGEN LAURENT
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Patent Agency Ranking
公开(公告)号：FR2638869B1
公开(公告)日：1990-12-21
申请号：FR8814707
申请日：1988-11-10
Applicant: SGS THOMSON MICROELECTRONICS
Inventor： FRUHAUF SERGE , SOURGEN LAURENT
Abstract: The disclosure concerns the safety of the confidential information contained in integrated circuits. In a certain number of integrated circuit applications and, more particularly, in the circuits contained in cards known as "chip cards", it is necessary to prohibit access by unauthorized persons to confidential information stored in a memory of the circuit. To prevent the fraudulent practice of examining the current consumption at the terminals of the integrated circuit during an operation of reading or writing in the memory, a protection circuit is used. This protection circuit actuates the simulation, according to a pseudo-random sequence generated by a generator, of current consumption values identical to those of real memory cells.
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公开(公告)号：FR2772967B1
公开(公告)日：2004-01-02
申请号：FR9716433
申请日：1997-12-18
Applicant: SGS THOMSON MICROELECTRONICS
Inventor： PIO FEDERICO , ZATELLI NICOLA , SOURGEN LAURENT , LISART MATHIEU
IPC: G11C16/02 , H01L21/8247 , H01L27/02 , H01L27/115 , H01L29/788 , H01L29/792 , G11C5/00 , G06F12/14
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公开(公告)号：DE69600376T2
公开(公告)日：1998-10-29
申请号：DE69600376
申请日：1996-10-24
Applicant: SGS THOMSON MICROELECTRONICS
Inventor： WUIDART SYLVIE , SOURGEN LAURENT
Abstract: The detection circuit has a pulse generator, which has a counter incrementing the pulse length of each pulse sent out. The pulse (Se) is applied to the integrated circuit via a snake shaped metallising line (2). The line forms a pass band filter with the passivation layer, and thus the short pulses are not received at the receiver (Sd) whilst longer pulses are. A correctly passivated integrated circuit can thus be determined from a tolerance threshold around the critical cut off pulse lengths.
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公开(公告)号：DE69600148T2
公开(公告)日：1998-04-30
申请号：DE69600148
申请日：1996-03-19
Applicant: SGS THOMSON MICROELECTRONICS
Inventor： SOURGEN LAURENT , WUIDART SYLVIE
Abstract: The method involves using a high-voltage generator (1) and regulator (2) delivering the write pulse (Ve) to the memory address decoder (5) in response to a command (3) from a counter (9) initialised by a pseudo-random number generator (8). A microprocessor ( mu p) decodes a write instruction received via input/output signals (IO1,IO2) and reads the random number which is decremented to 1 at the rate of the clock (Clk). A constant delay between the external write command and the end-of-write signal is held in a memory (10) which activates another counter (11) and is programmed for each circuit.
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公开(公告)号：FR2723223A1
公开(公告)日：1996-02-02
申请号：FR9409485
申请日：1994-07-29
Applicant: SGS THOMSON MICROELECTRONICS SA
Inventor： WUIDART SYLVIE , SOURGEN LAURENT
Abstract: The method involves using an executable code generator for discriminating between program instructions and program data, and for bit-scrambling the instructions. The resulting code is loaded into a programmable memory connected by the data bus to a controller. Program code is sent in scrambled form over the data bus, and is de-scrambled by a controller (DBR1,RI) for delivery to a processor (UP). A re-writable memory clears data, which is carried on the data bus and scrambles (DBR2,DBR3) data for storage. The data is unscrambled when read from storage. The scrambling algorithms for program code and for data are different.
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