公开(公告)号：EP0621604A1

公开(公告)日：1994-10-26

申请号：EP93830173.6

申请日：1993-04-23

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Bez, Roberto ,  Fratin, Lorenzo ,  Maurelli, Alfonso ,  Cantarelli, Daniele ,  Ghezzi, Paolo

IPC: G11C16/06

CPC classification number: G11C16/3409 ,  G11C16/16 ,  G11C16/3404

Abstract: A method for recovering flash-EEPROM memory cells (MC) with low threshold voltage is described. The method provide for the simultaneous application of a first voltage with a first prescribed value (V D ) and of a second voltage with a second prescribed value (V G ) to drain regions (D) of each of said memory cells (MC) and to gate regions (G) of the memory cell (MC) for a prescribed time interval suitable for submitting said memory cells (MC) to a prescribed threshold voltage shift. A reference ground voltage (GND) is concurrently applied to source regions (S) of said memory cells (MC).

Abstract translation: 描述了一种用于回收快闪EEPROM的存储单元用低阈值电压的方法（MC）。 该方法提供与第一规定值（VD）的第一电压的同时施加，并与一个第二规定值（VG）的第二电压的每一个所述存储单元的区域（D）（MC）和漏极到栅极 适合于提交所述存储单元（MC），以规定的阈值电压偏移规定的时间间隔存储单元（MC）的区域（G）。 参考地电压（GND）被并行地施加到所述存储器单元的源极区域（S）（MC）。

公开(公告)号：EP0786778A1

公开(公告)日：1997-07-30

申请号：EP96830024.4

申请日：1996-01-24

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Villa, Corrado ,  Bez, Roberto ,  Cantarelli, Daniele ,  Dallabora, Marco

IPC: G11C16/06

CPC classification number: G11C16/14

Abstract: A method for erasing an electrically programmable and erasable non-volatile memory cell having a control electrode, an electrically-insulated electrode and a first electrode, provides for coupling the control electrode to a first voltage supply, coupling the first electrode to a second voltage supply, the first voltage supply and the second voltage supply being suitable to cause tunneling of electric charges between the electrically-insulated electrode and the first electrode. The method provides for a constant current to flow between the second voltage supply and the first electrode of the memory cell for at least part of an erasing time of the memory cell, the constant current having a prescribed value.

Abstract translation: 一种用于在电可编程和可擦除的具有控制电极，在电绝缘的电极和第一电极的非易失性存储器单元擦除方法，提供用于控制电极耦合到第一电压源，所述第一电极耦合到第二电压供应 时，第一电源电压和第二电压供应适于引起的电绝缘电极和第一电极之间的电荷隧穿。 该方法提供了恒定的电流到所述第二电源电压和所述存储单元的第一电极之间，用于的存储单元的擦除时间的至少一部分流动，恒定电流具有一个预定值。

公开(公告)号：EP0772246A1

公开(公告)日：1997-05-07

申请号：EP95830459.4

申请日：1995-10-31

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Bez, Roberto ,  Camerlenghi, Emilio

IPC: H01L29/92 ,  H01L29/94

CPC classification number: H01L28/40 ,  H01L29/94

Abstract: The invention relates to a high-capacitance capacitor (1) which is monolithically integratable on a semiconductor substrate (3) doped with a first type (P) of dopant and accomodating a diffusion well (4) which is doped with a second type (N) of dopant and has a first active region (5) formed therein.
A layer (6) of gate oxide is deposited over the diffusion well (4) which is covered with a first layer (POLY1) of polycrystalline silicon and separated from a second layer (POLY2) of polycrystalline silicon by an interpoly dielectric layer (7).
Advantageously, the high-capacitance capacitor (1) of the invention comprises a first capacitor element (C1) having the first (POLY1) and second (POLY2) layers of polycrystalline silicon as its conductive plates, and the interpoly dielectric layer (7) as the isolation dielectric, and a second capacitor element (C2) having the first layer (POLY1) of polycrystalline silicon and the diffusion well (4) as its conductive plates and the gate oxide layer (6) as the isolation dielectric.

Abstract translation: 本发明涉及一种高容量电容器（1），其可单片集成在掺杂有第一类型（P）掺杂剂的半导体衬底（3）上，并且容纳扩散阱（4），该扩散阱掺杂有第二类型（N ），并且其中形成有第一有源区（5）。 栅极氧化物层（6）沉积在扩散阱（4）上，扩散阱（4）被多晶硅的第一层（POLY1）覆盖，并通过多晶硅介电层（7）与多晶硅的第二层（POLY2）分离， 。 有利地，本发明的大容量电容器（1）包括具有第一（POLY1）和第二（POLY2）多晶硅层作为其导电板的第一电容器元件（C1），并且所述多晶硅绝缘层（7）为 隔离电介质和具有多晶硅的第一层（POLY1）和作为其导电板的扩散阱（4）和作为隔离电介质的栅极氧化物层（6）的第二电容器元件（C2）。