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    Flash EEPROM with on-chip erase source voltage generator
    3.
    发明公开
    Flash EEPROM with on-chip erase source voltage generator 失效
    闪存EEPROM芯片-Löschung-Source-Spannungs发电机

    公开(公告)号：EP0756286A1

    公开(公告)日：1997-01-29

    申请号：EP95830317.4

    申请日：1995-07-24

    Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

    Inventor： Dallabora, Marco ,  Villa, Corrado ,  Bettini, Luigi

    IPC: G11C16/06 ,  G11C5/14

    CPC classification number: G11C16/16 ,  G11C5/147

    Abstract: A Flash EEPROM comprises negative voltage generator means (8) for generating a negative voltage to be supplied to control gate electrodes (CG) of memory cells (2) for erasing the memory cells (2). The Flash EEPROM comprises first positive voltage generator means (10) for generating a first positive voltage (VO), independent from an external power supply (VCC) of the Flash EEPROM, to be supplied to source regions (S) of the memory cells (2) during erasing.

    Abstract translation: 闪存EEPROM包括负电压发生器装置（8），用于产生用于擦除存储单元（2）的存储单元（2）的控制栅电极（CG）的负电压。 闪存EEPROM包括用于产生独立于闪存EEPROM的外部电源（VCC）的第一正电压（VO）的第一正电压发生器装置（10），以提供给存储器单元的源极区域（S） 2）擦除期间。

    A data output stage of the buffer type, having reduced noise to ground, for logic circuits of the CMOS type
    4.
    发明公开
    A data output stage of the buffer type, having reduced noise to ground, for logic circuits of the CMOS type 失效
    Datenusgabestufe des PuffertypsfürCMOS-Logikschaltungen mit vermindertemStörgeräuschgegenüberMasse。

    公开(公告)号：EP0455002A2

    公开(公告)日：1991-11-06

    申请号：EP91105323.9

    申请日：1991-04-04

    Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

    Inventor： Rolandi, Paolo ,  Maccalli, Marco ,  Dallabora, Marco

    IPC: H03K19/0185 ,  H03K19/003

    CPC classification number: H03K19/00361

    Abstract: A data output stage (1) of the buffer type for CMOS logic circuits, being of the type having at least one pair of MOS transistors (M1,M2) associated to drive an output node (3) of said stage (1), comprises first (8) and second (9) feedback loops which are structurally independent and respectively connected between said node (3) and a corresponding gate electrode (G1,G2) of each transistor (M1,M2) to pre-charge said output node (3) at a predetermined voltage value and reduce the noise to ground during the switching phase.

    Abstract translation: 用于CMOS逻辑电路的缓冲器类型的数据输出级（1）具有与驱动所述级（1）的输出节点（3）相关联的至少一对MOS晶体管（M1，M2）的类型，包括 第一（8）和第二（9）反馈回路，其在结构上独立且分别连接在所述节点（3）和每个晶体管（M1，M2）的对应的栅电极（G1，G2）之间，以对所述输出节点 3）处于预定电压值，并且在开关阶段期间将噪声降低到接地。

    Method of biasing a nonvolatile flash-EEPROM memory array
    6.
    发明公开
    Method of biasing a nonvolatile flash-EEPROM memory array 失效
    Verfahren zur Vorspannung einernichtflüchtigen闪存EEPROM - Speicheranordnung。

    公开(公告)号：EP0616333A1

    公开(公告)日：1994-09-21

    申请号：EP93830110.8

    申请日：1993-03-18

    Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

    Inventor： Campardo, Giovanni ,  Crisenza, Giuseppe ,  Dallabora, Marco

    IPC: G11C16/04 ,  G11C16/06

    CPC classification number: G11C16/04 ,  G11C16/0416 ,  G11C16/30

    Abstract: To reduce the read and write errors caused by depleted memory array cells being turned on even when not selected, the nonselected memory cells are so biased as to present a floating terminal and a terminal at a positive voltage with respect to the substrate region. In this way, the threshold voltage of the above cells (the minimum voltage between the gate and source terminals for the cell to be turned on) increases due to the "body effect", whereby the threshold voltage depends, among other things, on the voltage drop between the cell terminal operating as the source and the substrate, and increases alongside an increase in the voltage drop.

    Abstract translation: 为了减少即使未被选择也导致耗尽的存储器阵列单元导致的读取和写入错误，非选择的存储单元被偏置以使浮动端子和端子相对于衬底区域处于正电压。 以这种方式，由于“体效应”，上述单元的阈值电压（用于导通的单元的栅极和源极端子之间的最小电压）增加，由此阈值电压取决于 电池端子作为源极和基板之间的电压降，并且随着电压降的增加而增加。

    A data output stage of the buffer type, having reduced noise to ground, for logic circuits of the CMOS type
    9.
    发明公开
    A data output stage of the buffer type, having reduced noise to ground, for logic circuits of the CMOS type 失效
    缓冲器类型的数据输出级，具有减少噪声的接地，用于CMOS类型的逻辑电路

    公开(公告)号：EP0455002A3

    公开(公告)日：1991-11-21

    申请号：EP91105323.9

    申请日：1991-04-04

    Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

    Inventor： Rolandi, Paolo ,  Maccalli, Marco ,  Dallabora, Marco

    IPC: H03K19/0185 ,  H03K19/003

    CPC classification number: H03K19/00361

    Abstract: A data output stage (1) of the buffer type for CMOS logic circuits, being of the type having at least one pair of MOS transistors (M1,M2) associated to drive an output node (3) of said stage (1), comprises first (8) and second (9) feedback loops which are structurally independent and respectively connected between said node (3) and a corresponding gate electrode (G1,G2) of each transistor (M1,M2) to pre-charge said output node (3) at a predetermined voltage value and reduce the noise to ground during the switching phase.

    Abstract translation: 用于CMOS逻辑电路的缓冲器类型的数据输出级（1）具有与驱动所述级（1）的输出节点（3）相关联的至少一对MOS晶体管（M1，M2）的类型，包括 第一（8）和第二（9）反馈回路，其在结构上独立且分别连接在所述节点（3）和每个晶体管（M1，M2）的对应的栅电极（G1，G2）之间，以对所述输出节点 3）处于预定电压值，并且在开关阶段期间将噪声降低到接地。

    EPROM memory using programming voltages taken from a single low voltage power supply
    10.
    发明公开
    EPROM memory using programming voltages taken from a single low voltage power supply 失效
    EPROM存储器，其使用从单个低压电源编程电压萃取。

    公开(公告)号：EP0341768A2

    公开(公告)日：1989-11-15

    申请号：EP89201022.4

    申请日：1989-04-20

    Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

    Inventor： Gastaldi, Roberto ,  Dallabora, Marco ,  Casagrande, Giulio

    IPC: G11C17/00

    CPC classification number: G11C16/0416 ,  G11C16/30

    Abstract: The EPROM memory comprising a semiconductor substrate (1) with source (3) drain (2) and channel (4) areas, a control gate (5) and a floating gate (6) uses for programming a drain voltage no higher than the low power supply voltage (Vcc) employed for normal operation of the memory and a control gate voltage taken from said power supply voltage (Vcc) through a voltage booster (8).

    Abstract translation: 该EPROM存储器，包括：半导体衬底（1），源极（3）漏（2）和信道（4）的区域，控制栅极（5）及浮动栅极（6）使用对于比低编程漏极电压不高于 对于正常操作所述存储器和从所述电源电压（Vcc）通过升压器（8）截取的控制栅极电压的使用电源电压（Vcc）。

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