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1.发明授权A monolithic integrated circuit, particularly of either the MOS or CMOS type, and method of manufacturing same 失效独特的集成电路，特别是MOS或CMOS型，及其制造方法
公开(公告)号：EP0226549B1
公开(公告)日：1990-08-29
申请号：EP86830293.6
申请日：1986-10-09
Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.
Inventor： Maggioni, Franco , Baldi, Livio , Cappelletti, Paolo Giuseppe
CPC classification number: H01L27/0688 , H01L21/76889 , H01L23/528 , H01L23/53271 , H01L2924/0002 , Y10S148/019 , Y10S148/106 , Y10S148/136 , H01L2924/00
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2.发明公开Process for making structures including E2PROM nonvolatile memory cells with self-aligned layers of silicon and associated transistors 失效一种用于制造结构，包括EEPROM型的非易失性存储器单元，具有自对准硅层和相关联的晶体管的方法。
公开(公告)号：EP0255159A2
公开(公告)日：1988-02-03
申请号：EP87201211.7
申请日：1987-06-24
Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.
Inventor： Maggioni, Franco , Riva, Carlo
IPC: H01L21/82
CPC classification number: H01L27/11526 , H01L27/105 , H01L27/11529
Abstract: The process provides for obtaining in the areas intended for the formation of the transistors windows (9, 20, 10) in the intermediate oxide layer (5) between the two silicon layers (4, 11) and, before final etching of the two silicon layers (4, 11) and the intermediate oxide (5), application of a mask formed in such a manner as to superimpose on the second silicon layer (11) in the transistor areas coverings (13, 26, 14) wider than the corresponding windows (9, 20, 10) of the
intermediate oxide layer (5).Abstract translation: 的方法提供了两个硅层（4,11）之间，在用于在所述中间氧化物层（5）形成的晶体管的窗口（9，20，10）的区域获得，这两个硅的最终蚀刻之前 层（4，11）和所述中间氧化物（5），在寻求以在晶体管区域覆盖物（13，26，14）的第二硅层（11）上叠加的方式形成的掩模的应用抵抗比相应的 中间氧化物层的窗口（9，20，10）（5）。 Ť
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Patent Agency Ranking3.发明公开Method for ion implant programming NMOS read-only memories and NMOS read-only memory obtained thereby 失效由NMOS的离子注入编程的方法，只读存储器和一个NMOS只读存储器，从而获得。
公开(公告)号：EP0227965A2
公开(公告)日：1987-07-08
申请号：EP86116625.4
申请日：1986-11-29
Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.
Inventor： Cappelletti, Paolo Giuseppe , Maggioni, Franco
IPC: H01L27/10
CPC classification number: H01L27/112
Abstract: The method for ion implant programing NMOS read-only memories comprises the step of increasing the concentration of boron in the channel only proximate to the source junction of the NMOS devices of the memory which are to be programed 'off'. In this manner it is possible to increase the threshold voltage of these devices without reducing the breakdown voltage thereof, so as to obtain a reliable operation of the device or memory element even for very-large-scale-integration circuits, with a reduced thickness of oxide.
Abstract translation: 用于离子注入编程NMOS只读存储器的方法，包括在所述通道仅靠近所述存储器的NMOS器件哪些是源结增加硼的浓度的步骤，以进行编程“关闭”。 以这种方式，能够提高合成装置的阈值电压，而不会降低它们的击穿电压，以便获得可靠的操作的设备或存储元件的即使是非常大规模集成电路，具有减小的厚度 氧化物。
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4.发明授权Method for ion implant programming NMOS read-only memories and NMOS read-only memory obtained thereby 失效用于离子注入NMOS只读存储器和NMOS只读存储器的方法
公开(公告)号：EP0227965B1
公开(公告)日：1992-08-19
申请号：EP86116625.4
申请日：1986-11-29
Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.
Inventor： Cappelletti, Paolo Giuseppe , Maggioni, Franco
IPC: H01L27/10
CPC classification number: H01L27/112
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5.发明公开Process for making structures including E2PROM nonvolatile memory cells with self-aligned layers of silicon and associated transistors 失效制备结构的方法，包括具有自对准的硅和相关晶体管层的E2PROM非易失性记忆体
公开(公告)号：EP0255159A3
公开(公告)日：1989-11-15
申请号：EP87201211.7
申请日：1987-06-24
Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.
Inventor： Maggioni, Franco , Riva, Carlo
IPC: H01L21/82
CPC classification number: H01L27/11526 , H01L27/105 , H01L27/11529
Abstract: The process provides for obtaining in the areas intended for the formation of the transistors windows (9, 20, 10) in the intermediate oxide layer (5) between the two silicon layers (4, 11) and, before final etching of the two silicon layers (4, 11) and the intermediate oxide (5), application of a mask formed in such a manner as to superimpose on the second silicon layer (11) in the transistor areas coverings (13, 26, 14) wider than the corresponding windows (9, 20, 10) of the
intermediate oxide layer (5).-
6.发明授权Process for making structures including E2PROM nonvolatile memory cells with self-aligned layers of silicon and associated transistors 失效制备结构的方法，包括具有自对准的硅和相关晶体管层的E2PROM非易失性存储细胞
公开(公告)号：EP0255159B1
公开(公告)日：1993-09-15
申请号：EP87201211.7
申请日：1987-06-24
Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.
Inventor： Maggioni, Franco , Riva, Carlo
IPC: H01L21/82
CPC classification number: H01L27/11526 , H01L27/105 , H01L27/11529
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7.发明公开A monolithic integrated circuit, particularly of either the MOS or CMOS type, and method of manufacturing same 失效一种单片集成电路，尤其是的MOS或CMOS类型，和方法，用于其生产。
公开(公告)号：EP0226549A1
公开(公告)日：1987-06-24
申请号：EP86830293.6
申请日：1986-10-09
Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.
Inventor： Maggioni, Franco , Baldi, Livio , Cappelletti, Paolo Giuseppe
CPC classification number: H01L27/0688 , H01L21/76889 , H01L23/528 , H01L23/53271 , H01L2924/0002 , Y10S148/019 , Y10S148/106 , Y10S148/136 , H01L2924/00
Abstract: A monolithic integrated circuit of either the MOS or CMOS type comprises an intermediate layer (8) of polycrystalline silicon, a layer (9) of a silicide of a refractory metal overlying said polycrystalline silicon layer (8), and regions (8a) of preset area and preset paths (9a) formed in the polycrystalline silicon layer (8) and the silicide layer (9); the preset area regions (8a) and preset paths (9a) forming respectively high resistivity resistances and low resistivity interconnection lines for an intermediate connection level.
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