公开(公告)号：EP0757355A1

公开(公告)日：1997-02-05

申请号：EP95830347.1

申请日：1995-07-31

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Calligaro, Cristiano ,  Daniele, Vincenzo ,  Gastaldi, Roberto ,  Manstretta, Alessandro ,  Telecco, Nicola ,  Torelli, Guido

IPC: G11C11/56

CPC classification number: G11C11/5642 ,  G11C11/5621 ,  G11C2211/5632 ,  G11C2211/5633

Abstract: A method for sensing multiple-levels non-volatile memory cells which can take one programming level among a plurality of m=2 n (n > = 2) different programming levels, provides for biasing a memory cell (MC) to be sensed in a predetermined condition, so that the memory cell (MC) sinks a cell current (IC) with a value belonging to a discrete set of m distinct cell current values (IC0-IC15), each cell current value (IC0-IC15) corresponding to one of said programming levels. The sensing method also provides for: simultaneously comparing the cell current (IC) with a prescribed number of reference currents (IR1,IR2,IR3) having values comprised between a minimum value and a maximum value of said discrete set of m cell current values (IC0-IC15) and dividing said discrete set of m cell current values (IC0-IC15) in a plurality of sub-sets of cell current values, for determining the sub-set of cell current values to which the cell current (IC) belongs; repeating step a) for the sub-set of cell current values to which the cell current (IC) belongs, until the sub-set of cell current values to which the cell current (IC) belongs comprises only one cell current value, which is the value of the current (IC) of the memory cell (MC) to be sensed.

Abstract translation: 这可能需要m的多元性中的一个编程电平，用于感测多电平非易失性存储器单元的方法= 2 （N> = 2）不同的编程的水平，提供了一种用于偏置的存储单元（MC）被感测到的 在预定条件下，所以没有存储器单元（MC）汇的单元电流（IC）与值属于一组离散的m个不同的单元电流值的（IC 0-IC15），每个单元的电流值（IC 0-IC15）对应 与所述编程水平之一。 所述sensingmethod因此提供用于：同时单元电流（IC）与参考电流（IR1，IR2，IR3）的最小值和所述离散组m个单元电流值的最大值之间由具有值的规定数量的比较（ IC 0-IC15）和将所述离散组m个单元电流值的（IC 0-IC15）（在子集的单元电流值的复数，用于确定性采矿子集小区的电流值，以该单元电流IC）属于 ; 重复步骤a）用于单元电流值的子集到的电池电流（IC）所属直到单元电流值的子集到的电池电流（IC）属于仅包括一个单元电流值，在所有其 要被感测的存储单元（MC）的电流（IC）的值。

公开(公告)号：EP0559995A1

公开(公告)日：1993-09-15

申请号：EP92830115.9

申请日：1992-03-11

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Gastaldi, Roberto

IPC: G11C16/06

CPC classification number: G11C8/08 ,  G11C16/08

Abstract: An integrated word line decoding circuit utilizes a voltage transferring inverter whose driver transistor may be biased independently of the other transistors of the same type of conductivity of the integrated circuit by forming it in a first region having the same type of conductivity of the semiconducting substrate of the integrated circuit and which is entirely contained within a second region having an opposite type of conductivity into which the complementary load transistor of the inverter is formed. The circuit is capable of transferring positive voltages (e.g. during reading and programming) and a negative voltage (e.g. during erasing) to the word lines, while being readily integratable and requiring a small area.

Abstract translation: 集成字线解码电路利用电压转换逆变器，其驱动晶体管可以被独立于集成电路的相同类型的导电性的其它晶体管而被偏置，其形成在具有与半导体衬底相同类型的导电性的第一区域中 该集成电路完全包含在形成有逆变器的互补负载晶体管的相反导电类型的第二区域内。 该电路能够将正电压（例如在读取和编程期间）以及负电压（例如在擦除期间）传送到字线，同时易于集成并且需要较小的面积。

公开(公告)号：EP0341768A3

公开(公告)日：1991-10-02

申请号：EP89201022.4

申请日：1989-04-20

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Gastaldi, Roberto ,  Dallabora, Marco ,  Casagrande, Giulio

IPC: G11C17/00

CPC classification number: G11C16/0416 ,  G11C16/30

Abstract: The EPROM memory comprising a semiconductor substrate (1) with source (3) drain (2) and channel (4) areas, a control gate (5) and a floating gate (6) uses for programming a drain voltage no higher than the low power supply voltage (Vcc) employed for normal operation of the memory and a control gate voltage taken from said power supply voltage (Vcc) through a voltage booster (8).

Abstract translation: EPROM存储器包括具有源极（3）漏极（2）和沟道（4）区域的半导体衬底（1），控制栅极（5）和浮动栅极（6）用于对不高于低 用于存储器的正常操作的电源电压（Vcc）和通过电压增压器（8）从所述电源电压（Vcc）获取的控制栅极电压。

公开(公告)号：EP0646924A1

公开(公告)日：1995-04-05

申请号：EP93830403.7

申请日：1993-09-30

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Calligaro, Cristiano ,  Gastaldi, Roberto ,  Malcovati, Piero ,  Torelli, Guido

IPC: G11C5/00 ,  H02M3/07

CPC classification number: H02M3/07 ,  G11C5/145

Abstract: A circuit for generating positive and negative boosted voltages, comprising first (El-pos) and second (El-neg) voltage booster circuits, respectively for positive and negative voltages, which have output terminals interconnected at a common node (N).
It comprises two tristate logic gate circuits for coupling said voltage booster circuits to a positive supply voltage generator (Vdd,GND) and additional tristate logic gate circuits for driving the phases of charge pump circuits incorporated to the booster circuits.
This voltage generating circuit may be integrated in single-well CMOS technology.

Abstract translation: 一种用于生成正和负电路升压的电压，其包括第一发光（EL-POS）和第二致发光（EL-NEG）电压升压电路，用于分别正和负电压，其具有在一个共同的节点（N）相互连接的输出端子。 它包括两个三态逻辑门电路，用于耦合所述电压升压电路到正电源电压发生器（VDD，GND）和另外的三态逻辑门电路，用于驱动的​​方式并入到升压电路的电荷泵电路的相位。 该电压产生电路可以被集成在单阱CMOS技术。

公开(公告)号：EP0811986A1

公开(公告)日：1997-12-10

申请号：EP96830318.0

申请日：1996-06-05

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Calligaro, Cristiano ,  Gastaldi, Roberto ,  Manstretta, Alessandro ,  Cappelletti, Paolo ,  Torelli, Guido

IPC: G11C11/56

CPC classification number: G11C11/5621 ,  G11C11/5642 ,  G11C2211/5632 ,  G11C2211/5634

Abstract: A page-mode semiconductor memory device comprises a matrix (1) of memory cells (MC') arranged in rows (R) and columns (C), each row (R) forming a memory page (MP1-MPn) of the memory device and comprising at least one group (MW1,MW2-MW2m-1,MW2m) of memory cells (MC'), memory page selection means (2) for selecting a row (R) of the matrix (1), and a plurality of sensing circuits (3') each one associated to a respective column (C) of the matrix. The memory cells (MC') are multiple-level memory cells which can be programmed in a plurality of c=2 b (b>1) programming states to store b information bits, and the sensing circuits (3') are serial-dichotomic sensing circuits capable of determining, in a number b of consecutive approximation steps, the b information bits stored in the memory cells (MC'), at each step one of said b information bits being determined, said at least one group (MW1,MW2-MW2m-1,MW2m) of memory cells (MC') of a row (R) forming a number b of memory words of a memory page (MP1-MPn).

Abstract translation: 页模式半导体存储器件包括以行（R）和列（C）排列的存储单元（MC'）的矩阵（1），每行（R）形成存储器件的存储器页（MP1-MPn） 并且包括用于选择矩阵（1）的行（R）的至少一个组（MW1，MW2-MW2m-1，MW2m）的存储器单元（MC'），存储器页选择装置（2） 每个检测电路（3'）与矩阵的相应列（C）相关联。 存储单元（MC'）是可以以多个c = 2（b> 1）编程状态编程的多级存储器单元，用于存储b个信息位，并且感测电路（3'）是串行 所述至少一个组（MW1）包括：在所述b个信息比特中的每个步骤中确定所述b个信息比特中的每个步骤中存储的存储单元（MC'）中的b个信息比特， ，MW2-MW2m-1，MW2m）形成存储器页（MP1-MPn）的存储器字数b的行（R）的存储器单元（MC'）。

公开(公告)号：EP0793238A1

公开(公告)日：1997-09-03

申请号：EP96830088.9

申请日：1996-02-29

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Beverina, Bruno ,  Cappelletti, Paolo ,  Gastaldi, Roberto

IPC: G11C16/06

CPC classification number: G11C16/14 ,  G11C16/12

Abstract: A device incorporating electrically programmable non-volatile memory cells for a small number of programming cycles, in which an individual cell is impressed, both during the write step and the erase step, a bias condition such that a charge flow can only occur between the drain region and the gate dielectric, and vice versa.

Abstract translation: 一种装置，包含电可编程的非易失性存储器单元用于少量编程周期，在其中个体单元印象深刻，在写入步骤和所述擦除步骤中，偏置条件的搜索没有电荷流动只能漏极之间都会出现 区域和栅极电介质，并且反之亦然。

公开(公告)号：EP0735542A1

公开(公告)日：1996-10-02

申请号：EP95830127.7

申请日：1995-03-31

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Calligaro, Cristiano ,  Daniele, Vincenzo ,  Gastaldi, Roberto ,  Manstretta, Alessandro ,  Telecco, Nicola ,  Torelli, Guido

IPC: G11C11/56

CPC classification number: G11C11/5642 ,  G11C11/5621 ,  G11C2211/5631

Abstract: Reading circuit for multilevel non-volatile memory cell devices comprising for each cell to be read a selection line with which is associated a load (ML) and a decoupling and control stage (MF) with a feedback loop (INV) which stabilizes the voltage on a circuit node (F) of the selection line.
To this node are connected the current replica circuit means which are controlled by the feedback loop (INV).
These include loads (M1,M2,M3) and circuit elements (MC1,MC2,MC3) homologous to those associated with the selection line of the memory cell and have output interface circuit means (A,B,C) for connection to current comparator circuit means.

Abstract translation: 用于多电平非易失性存储单元器件的读取电路，包括用于读取与负载（ML）和解耦和控制级（MF）相关联的选择线的每个单元与具有稳定电压的反馈回路（INV） 选择线的电路节点（F）。 该节点连接由反馈回路（INV）控制的当前复制电路装置。 这些包括与存储器单元的选择线相关联的负载（M1，M2，M3）和电路元件（MC1，MC2，MC3），并具有用于连接到电流比较器的输出接口电路装置（A，B，C） 电路方式。

公开(公告)号：EP0734024A1

公开(公告)日：1996-09-25

申请号：EP95830110.3

申请日：1995-03-23

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Calligaro, Cristiano ,  Daniele, Vincenzo ,  Gastaldi, Roberto ,  Manstretta, Alessandro ,  Telecco, Nicola ,  Torelli, Guido

IPC: G11C11/56

CPC classification number: G11C11/5621 ,  G11C11/5642 ,  G11C2211/5632

Abstract: A sensing circuit for serial dichotomic sensing of multiple-levels memory cells (MC) which can take one programming level among a plurality of m=2 n (n >= 2) different programming levels, comprises biasing means for biasing a memory cell (MC) to be sensed in a predetermined condition, so that the memory cell (MC) sinks a cell current (IC) with a value belonging to a plurality of m distinct cell current values (IC0-IC3), each cell current value (IC0-IC3) corresponding to one of the programming levels, a current comparator (1) for comparing the cell current (IC) with a reference current (IR) generated by a variable reference current generator (G), and a successive approximation register (2) supplied with an output signal (CMP) of the current comparator (1) and controlling the variable reference current generator (G). The variable reference current generator comprises an offset current generator (Ioff) permanently coupled to the current comparator (1), and m-2 distinct current generators (IR0,IR1), independently activatable by the successive approximation register (2), each one generating a current (IC1,IC2) equal to a respective one of the plurality of cell current values (IC0-IC3).

Abstract translation: 一种用于多级存储器单元（MC）的串行二分感测的感测电路，其可以在多个m = 2n（n> = 2）不同编程电平中取一个编程电平，包括用于偏置存储器单元 （MC），以使得存储单元（MC）以具有多个m个不同的单元电流值（IC0-IC3），每个单元电流值（IC0-IC3）的值吸收单元电流（IC） IC0-IC3），用于将电池电流（IC）与可变参考电流发生器（G）产生的参考电流（IR）进行比较的电流比较器（1）和逐次逼近寄存器（ 2）提供电流比较器（1）的输出信号（CMP）并控制可变参考电流发生器（G）。 可变参考电流发生器包括永久地耦合到电流比较器（1）的偏移电流发生器（Ioff）和由逐次逼近寄存器（2）独立激活的m-2个不同的电流发生器（IR0，IR1），每个发生器 等于多个单元电流值（IC0-IC3）中的相应一个的电流（IC1，IC2）。

公开(公告)号：EP0724266A1

公开(公告)日：1996-07-31

申请号：EP95830023.8

申请日：1995-01-27

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Calligaro, Cristiano ,  Daniele, Vincenzo ,  Gastaldi, Roberto ,  Manstretta, Alessandro ,  Torelli, Guido

IPC: G11C11/56

CPC classification number: G11C11/5642 ,  G11C11/5621 ,  G11C2211/5632

Abstract: A successive approximation method for sensing multiple-level non-volatile memory cells which can take one of m=2 n (n >=2) different programming levels, provides for biasing a memory cell (MC) to be sensed in a predetermined condition, so that the memory cell (MC) sinks a cell current (IC) with a value belonging to a plurality of m distinct cell current values (IC0-IC3;IC0-IC15), and for : a) comparing the cell current (IC) with a reference current (IR) which has a value comprised between a minimum value and a maximum value of said plurality of m cell current values (IC0-IC3;IC0-IC15), thus dividing said plurality of cell current values (IC0-IC3;IC0-IC15) into two sub-pluralities of cell current values, and determining the sub-plurality of cell current values to which the cell current (IC) belongs; b) repeating the step a) until the sub-plurality of cell current values to which the cell current (IC) belongs comprises only one cell current value, which is the value for the current (IC) of the memory cell (MC) to be sensed.

Abstract translation: 用于感测多级非易失性存储器单元逐次逼近方法，其可以采取m个= 2 （N> = 2）不同的编程的水平，提供了一种用于偏置的存储单元（MC）将被在预定的感测到的 条件，所以没有存储器单元（MC）汇的单元电流（IC）与值属于m个不同的单元电流值的多个（IC 0-IC3; IC 0-IC15），以及用于：1）将所述的单元电流（ IC）与参考电流（IR），其具有最小值和米单元电流值的所述多个（IC 0-IC3的最大值之间包含的值; IC 0-IC15），从而划分单元电流值的所述多个（IC 0 -IC3; IC 0-IC15）成细胞电流值的两个子多个，和确定性采矿到的电池电流（IC）所属的单元电流值的次多个; B）重复所述步骤a），直至至哪个单元电流（IC）属于仅包括一个单元电流值的单元电流值的次多个，所有这些是存储单元（MC），以用于当前（IC值） 进行检测。

公开(公告)号：EP0833340A1

公开(公告)日：1998-04-01

申请号：EP96830494.9

申请日：1996-09-30

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Calligaro, Cristiano ,  Rolandi, Paolo ,  Gastaldi, Roberto ,  Torelli, Guido

IPC: G11C7/00 ,  G11C11/56

CPC classification number: G11C7/062 ,  G11C7/06 ,  G11C7/065 ,  G11C11/5621 ,  G11C11/5642

Abstract: A read circuit for semiconductor memory cells, comprising first and second active elements (M sr ,M sm ) coupled to a supply line (Vdd) via at least a first switch (M1), wherein said first and second active elements are respectively connected, at first (outref) and second (outsel) circuit nodes, respectively, to a first (M LN ), whereby the active elements are coupled to a ground (gnd). These first and second circuit nodes are also connected to said ground through first (CR) and second (CM) capacitive elements, respectively, each having a switch (MPR, MPM) connected in parallel to the capacitive element.

Abstract translation: 一种用于半导体存储器单元的读取电路，包括经由至少第一开关（M1）耦合到电源线（Vdd）的第一和第二有源元件（Msr，Msm），其中所述第一和第二有源元件首先分别连接 （outref）和第二（外部）电路节点分配到第一（MLN），由此有源元件耦合到地（gnd）。 这些第一和第二电路节点也分别通过第一（CR）和第二（CM）电容元件连接到所述地，每个具有与电容元件并联连接的开关（MPR，MPM）。