公开(公告)号：EP0621604A1

公开(公告)日：1994-10-26

申请号：EP93830173.6

申请日：1993-04-23

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Bez, Roberto ,  Fratin, Lorenzo ,  Maurelli, Alfonso ,  Cantarelli, Daniele ,  Ghezzi, Paolo

IPC: G11C16/06

CPC classification number: G11C16/3409 ,  G11C16/16 ,  G11C16/3404

Abstract: A method for recovering flash-EEPROM memory cells (MC) with low threshold voltage is described. The method provide for the simultaneous application of a first voltage with a first prescribed value (V D ) and of a second voltage with a second prescribed value (V G ) to drain regions (D) of each of said memory cells (MC) and to gate regions (G) of the memory cell (MC) for a prescribed time interval suitable for submitting said memory cells (MC) to a prescribed threshold voltage shift. A reference ground voltage (GND) is concurrently applied to source regions (S) of said memory cells (MC).

Abstract translation: 描述了一种用于回收快闪EEPROM的存储单元用低阈值电压的方法（MC）。 该方法提供与第一规定值（VD）的第一电压的同时施加，并与一个第二规定值（VG）的第二电压的每一个所述存储单元的区域（D）（MC）和漏极到栅极 适合于提交所述存储单元（MC），以规定的阈值电压偏移规定的时间间隔存储单元（MC）的区域（G）。 参考地电压（GND）被并行地施加到所述存储器单元的源极区域（S）（MC）。

公开(公告)号：EP0856886A1

公开(公告)日：1998-08-05

申请号：EP97830029.1

申请日：1997-01-31

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Calegari, Camilla ,  Carrara, Anna ,  Fratin, Lorenzo ,  Riva, Carlo

IPC: H01L23/00 ,  H01L23/532

CPC classification number: H01L23/564 ,  H01L23/3171 ,  H01L23/5329 ,  H01L2924/0002 ,  Y10S438/958 ,  H01L2924/00

Abstract: A process for the formation of a device edge morphological structure (30) for protecting and sealing peripherally an electronic circuit integrated in a major surface (5) of a substrate of semiconductor material (6) is of the type that calls for formation above the major surface (5) of at least one dielectric multilayer (20) comprising a layer of amorphous planarizing material (22) having a continuous portion extending between two contiguous areas with a more internal first area (3') and a more external second area (4') in the morphological structure (30).
In accordance with the present invention inside the device edge morphological structure (30) in the substrate (6) is formed an excavation on the side of the major surface (5) the more internal first area (3') of the morphological structure (30) in a zone in which is present the continuous portion of the dielectric multilayer (20).

Abstract translation: 为集成在一个主表面的电子电路的保护和密封经外周为一个装置边缘的形态结构（30）的形成的方法，（5）的半导体材料的基片（6）是所述类型的那样呼叫为了形成上述的主要 至少一个电介质多层（20），包括无定形的平坦化材料的具有连续的部分中的两个相邻的区域之间延伸的具有多个内部第一区域（3“）的层（22）和多个外部的第二区域的表面（5）（4 “）（在形态结构30）。 在与在器件边缘的形态结构（30）内的本发明雅舞蹈的（6）在主表面的形态结构的侧面（5）的更内部的第一区域（3”）而形成的挖掘（30个基板 ）（在所有的区域，其存在于电介质多层20）的连续部分。

公开(公告)号：EP0798785A1

公开(公告)日：1997-10-01

申请号：EP96830175.4

申请日：1996-03-29

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Fratin, Lorenzo ,  Riva, Carlo

IPC: H01L29/49 ,  H01L29/78 ,  H01L21/336 ,  H01L21/8247

CPC classification number: H01L29/4983 ,  H01L21/28105 ,  H01L29/66492 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/7836

Abstract: A MOS transistor (1) capable of withstanding relatively high voltages is of a type integrated on a region (3) included in a substrate of semiconductor material, having conductivity of a first type (N) and comprising a channel region (7) intermediate between a first active region of source (4) and a second active region of drain (5). Both these regions (4 and 5) have conductivity of a second type (P) and extend from a first surface (6) of the substrate. The transistor (1) also has a gate which comprises at least a first polysilicon layer (8) overlying the first surface (6) at at least said channel region (7), to which it is coupled capacitively through a gate oxide layer (9).
According to the invention, the first polysilicon layer (8) includes a mid-portion (13) which only overlies said channel region (7) and has a first total conductivity (C1) of said first type (N), and a peripheral portion (14) with a second total conductivity (C2) differentiated from said first total conductivity (C1), which peripheral portion partly overlies said source and drain active regions (4 and 5) toward said channel region (7).

Abstract translation: 能够承受相对较高电压的MOS晶体管（1）是集成在包括在半导体材料的衬底中的区域（3）上的类型，其具有第一类型（N）的导电性并且包括位于第一类型（N）之间的沟道区域 源极（4）的第一有源区和漏极（5）的第二有源区。 这两个区域（4和5）都具有第二类型（P）的导电性并且从衬底的第一表面（6）延伸。 晶体管（1）还具有栅极，该栅极至少包括在至少所述沟道区（7）上覆盖第一表面（6）的第一多晶硅层（8），电容性地通过栅极氧化物层（9） ）。 根据本发明，第一多晶硅层（8）包括仅覆盖所述沟道区（7）并且具有所述第一类型（N）的第一总电导率（C1）的中间部分（13），并且周边部分 （14），其具有与所述第一总导电率（C1）不同的第二总导电率（C2），所述周边部分部分地覆盖所述源极和漏极有源区域（4和5）朝向所述沟道区域（7）。

公开(公告)号：EP0758129A1

公开(公告)日：1997-02-12

申请号：EP95830351.3

申请日：1995-08-02

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Fratin, Lorenzo ,  Ravazzi, Leonardo ,  Riva, Carlo

IPC: G11C16/06 ,  G11C5/14

CPC classification number: G11C16/30 ,  G11C5/147

Abstract: A Flash EEPROM comprises an array (1) of memory cells (MC) having a common source line (SL) connecting together source electrodes (S) of the memory cells (MC), said common source line (SL) being coupled to a positive potential (VPP) when the memory cells (MC) must be electrically erased, and resistive feedback means (R) coupled in series between said positive potential (VPP) and said common source line (SL). The Flash EEPROM comprises voltage limiting means (CL) coupled to said common source line (SL) for limiting the potential of the common source line (SL) to a prescribed maximum value (VCL) lower than said positive potential (VPP).

Abstract translation: 闪存EEPROM包括具有连接存储单元（MC）的源电极（S）的公共源极线（SL）的存储单元（MC）的阵列（1），所述公共源极线（SL）耦合到正极 必须电擦除存储器单元（MC）的电位（VPP）和串联耦合在所述正电位（VPP）和所述公共源极线（SL）之间的电阻反馈装置（R）。 闪存EEPROM包括耦合到所述公共源极线（SL）的电压限制装置（CL），用于将公共源极线（SL）的电位限制到低于所述正电位（VPP）的规定的最大值（VCL）。

公开(公告)号：EP0696050A1

公开(公告)日：1996-02-07

申请号：EP94830363.1

申请日：1994-07-18

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Fratin, Lorenzo ,  Ravazzi, Leonardo ,  Riva, Carlo

IPC: H01L21/00 ,  H01L21/336 ,  H01L29/10 ,  H01L29/788

CPC classification number: H01L29/66825 ,  H01L29/1045 ,  H01L29/7881

Abstract: A nonvolatile memory (40) having a cell (31) comprising an N⁺ type source region (24) and drain region (12) embedded in a P⁻ type substrate (4) and surrounded by respective P-pockets (26, 16). The drain and source P-pockets (16, 26) are formed in two different high-angle boron implantation steps designed to optimize implantation energy and dosage for ensuring scalability of the cell and avoiding impairment of the snap-back voltage. The resulting cell (31) also presents a higher breakdown voltage as compared with known cells.

Abstract translation: 嵌入在P A的非易失性存储器（40），具有包含N的细胞（31）<+>型源区（24）和漏区（12）< - >型衬底（4）和由respectivement P-凹槽围绕着（ 26，16）。 漏极和源极P-口袋（16，26）形成在设计用于优化的注入能量和剂量为确保电池的可扩展性和避免跳回电压的损害两个不同的高角度硼注入步骤。 因此所得到的细胞（31）呈现出更高的击穿电压与已知的细胞相比。 $$