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    SEMICONDUCTOR INTEGRATED CIRCUIT
    1.
    发明专利
    SEMICONDUCTOR INTEGRATED CIRCUIT 失效

    公开(公告)号：JP2000031425A

    公开(公告)日：2000-01-28

    申请号：JP17893899

    申请日：1999-06-24

    Applicant: SIEMENS AG ,  IBM

    Inventor： SCHREMS MARTIN ,  MANDELMAN JACK ,  HOEPFNER JOACHIM ,  SCHAEFER HERBERT ,  STENGL REINHARD

    IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

    Abstract: PROBLEM TO BE SOLVED: To reduce the rough surface on a side wall of a trench of a trench capacitor by forming the trench capacitor in the shape of a bottle with the lower part of the treanch being larger than the upper part and covering a collar and an epitaxial buried plate from inside with a node dielectric. SOLUTION: A trench capacitor 310 included in a DRAM cell 300 is formed in a silicon wafer substrate 301. A lower part of a trench has a larger diameter or width WL than the diameter or width WU of an upper part. The trench of such a shape is called a bottle trench. And, an epitaxial silicon (epi) layer 365 covers the lower part of the trench below a collar 368 from inside. The epi is doped with an n-type dopant such as As or P and is used as a buried plate of a capacitor. By covering the lower part of the trench by the epi layer from inside, the rough surface to be formed with a node dielectric can be reduced.

    BPSG REFLOW AND METHOD FOR SUPPRESSING PATTERN DISTORTION RELATED TO INTEGRATED CIRCUIT CHIP FORMED BY IT
    3.
    发明专利
    BPSG REFLOW AND METHOD FOR SUPPRESSING PATTERN DISTORTION RELATED TO INTEGRATED CIRCUIT CHIP FORMED BY IT 失效

    公开(公告)号：JPH10135326A

    公开(公告)日：1998-05-22

    申请号：JP27283597

    申请日：1997-10-06

    Applicant: IBM ,  SIEMENS AG

    Inventor： GAMBINO JEFFREY PETER ,  NGUYEN SON VAN ,  STENGL REINHARD

    IPC: H01L21/28 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

    Abstract: PROBLEM TO BE SOLVED: To increase the densities of borophosphate-silicate glass and an oxide existing on the glass before forming a pattern, by exposing the glass and undoped oxide to a high temperature before a line patterning step, a contact etching step, and an ion implanting step. SOLUTION: After a dielectric layer of borophosphate-silicate glass having fluidity is stuck to the surface of a substrate, another dielectric layer of a material having no fluidity is stuck to the surface of the glass layer. Then, contact etching and a high dose of ion implantation are performed so that an undoped oxide composed of SiO2 existing on the dielectric layer having no fluidity can be exposed to a junction activating annealing temperature, namely, a high annealing temperature of about 800 deg.C to 1,100 deg.C. After the ion implantation, contacts and lines are metallized by again exposing the contacts and lines to a high annealing temperature. Therefore, the densities of the borophosphate-silicate glass and SiO2 existing on the glass can be increased before forming a pattern.

    MANUFACTURE OF CAPACITOR FOR SEMICONDUCTOR DEVICE
    6.
    发明专利
    MANUFACTURE OF CAPACITOR FOR SEMICONDUCTOR DEVICE 失效

    公开(公告)号：JPH10242430A

    公开(公告)日：1998-09-11

    申请号：JP5912998

    申请日：1998-02-25

    Applicant: SIEMENS AG

    Inventor： FRANOSCH MARTIN DIPL PHYS ,  SCHAEFER HERBERT ,  STENGL REINHARD ,  LANGE GERRIT ,  LEHMANN VOLKER ,  WENDT HERMANN ,  REISINGER HANS DR

    IPC: H01L21/8242 ,  H01L27/108 ,  H01L29/94

    Abstract: PROBLEM TO BE SOLVED: To reduce manufacture cost by alternately forming layer rows which alternately have layers formed of silicon and layers containing germanium on a substrate, forming supporting patterns so that they cover the layer rows, selectively removing the layers containing germanium and forming dielectrics and the like on the surface of the supporting patterns. SOLUTION: An insulating layer 2 is formed on the substrate 1 and the layer strings where the layers 41 formed of silicon and the layers 42 containing germanium are alternately doped are formed on the surface of the insulating layer 2. Layer patterns 4' are formed so that the surface of the insulating layer 2 is exposed by anisotropic etching. The supporting patterns 5 covering the sides and the surfaces of the layer patterns 4' are formed by selective epitaxy. The part of the layers 42 containing germanium is removed by selective etching so that the layers 41 constituted of doped silicon and the supporting patterns remain. Then, the capacitor dielectrics 6 and a counter electrode 7 are formed on the surfaces of the layers 41 formed of doped silicon and the supporting patterns 5.

    MANUFACTURE OF CAPACITOR FOR SEMICONDUCTOR DEVICE
    7.
    发明专利
    MANUFACTURE OF CAPACITOR FOR SEMICONDUCTOR DEVICE 失效

    公开(公告)号：JPH10242429A

    公开(公告)日：1998-09-11

    申请号：JP5912898

    申请日：1998-02-25

    Applicant: SIEMENS AG

    Inventor： FRANOSCH MARTIN DIPL PHYS ,  HOENLEIN WOLFGANG ,  KLOSE HELMUT ,  LANGE GERRIT ,  LEHMANN VOLKER ,  REISINGER HANS DR ,  SCHAEFER HERBERT ,  STENGL REINHARD ,  WENDT HERMANN ,  WIDMANN DIETRICH

    IPC: H01L21/306 ,  H01L21/8242 ,  H01L27/108

    Abstract: PROBLEM TO BE SOLVED: To reduce manufacture cost by alternately forming a silicon layer and a layer containing germanium in a trench on a semiconductor substrate, forming a supporting pattern, removing the layer containing germanium and forming an electrode pattern. SOLUTION: A trench mask 13 is formed on the semiconductor substrate 12 and the trench is formed by etching. A dope region 15, the layer 16 containing germanium, the silicon layer 17 and the layer 18 containing germanium are formed in the trench. Then, a base part is removed and a polysilicon layer 20 becoming the supporting pattern is formed. Then, the upper part of the polysilicon layer 20 is etched back and the layers 16 and 18 containing germanium are removed by selective etching. Then, the electrode pattern 21 is formed. A memory dielectric 22 is formed on the surface of the electrode pattern 21, a counter electrode 23 by the polysilicon layer is formed so that the internal part of the trench is filled and a capacitor is formed. Furthermore, source/drain regions 24 are formed.

    INTEGRATED CIRCUIT WITH P-N JUNCTIONS WITH REDUCED DEFECTS
    8.
    发明申请
    INTEGRATED CIRCUIT WITH P-N JUNCTIONS WITH REDUCED DEFECTS 审中-公开
    INTEGRATED CIRCUIT WITH P-N转变WITH减少的缺陷

    公开(公告)号：WO0002249A3

    公开(公告)日：2000-03-16

    申请号：PCT/DE9901934

    申请日：1999-07-01

    Applicant: SIEMENS AG ,  STENGL REINHARD ,  FRANOSCH MARTIN ,  SCHAEFER HERBERT ,  LEHMANN VOLKER ,  REISINGER HANS ,  WENDT HERMANN

    Inventor： STENGL REINHARD ,  FRANOSCH MARTIN ,  SCHAEFER HERBERT ,  LEHMANN VOLKER ,  REISINGER HANS ,  WENDT HERMANN

    IPC: H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108 ,  H01L29/04

    CPC classification number: H01L27/10844 ,  H01L27/10805 ,  H01L29/045

    Abstract: The inventive integrated circuit comprises at least one first component with a structure to which defects may be adjacent and a second component with at least one p-n junction (Ü'), said components being situated next to each other in a substrate (1) whose defects extend in a defect plane (d) at least in sections. The crystal orientation of the substrate (1) in relation to the first component and the second component is chosen with the aim of keeping the defects on the surfaces without them intersecting the p-n junction (Ü'), in order to prevent undesirable leakage currents through the p-n junction (Ü'). The integrated circuit is especially a DRAM cell arrangement with extended retention time. The inventive integrated circuit is produced by mounting photo-resist masks of a known layout on the starting wafer, the masks being rotated in relation to a known starting wafer. Alternatively, photo-resist masks of a known layout can be mounted on a starting wafer in a conventional manner, the output wafer having a marking showing the course of the defect plane (d).

    Abstract translation: 所述集成电路装置包括至少在一个基片具有可以在邻近缺陷彼此相邻的结构，并且具有至少一个pn结（B“）的第二组分的第一组分（1）被布置，其至少缺陷部分中 缺陷电平（d）延伸。 被选择的衬底（1）相对于所述第一组分和所述第二组分的晶体取向，使得缺陷被记录在表面上而不被切断p-n结。 以这种方式，能够避免通过p-n结（B“）不希望的泄漏。 集成电路装置是特别具有增加的保留时间的DRAM单元的布置。 为了制备集成电路装置光刻胶掩模可以被安装在一个已知的晶片布局相对于扭转的已知的起始晶片的输出。 可替代地，光致抗蚀剂掩模的已知布局可以在输出晶片上以常规方式应用，但起始晶片具有示出的缺陷电平（d）的过程中的标签。

    DRAM STORAGE CAPACITOR
    9.
    发明申请
    DRAM STORAGE CAPACITOR 审中-公开
    存储器，用于电容器DRAM

    公开(公告)号：WO9965063A3

    公开(公告)日：2000-03-16

    申请号：PCT/DE9901454

    申请日：1999-05-12

    Applicant: SIEMENS AG ,  REISINGER HANS ,  LEHMANN VOLKER ,  STENGL REINHARD ,  WENDT HERMANN ,  LANGE GERRIT ,  BACHHOFER HARALD ,  FRANOSCH MARTIN ,  SCHAEFER HERBERT

    Inventor： REISINGER HANS ,  LEHMANN VOLKER ,  STENGL REINHARD ,  WENDT HERMANN ,  LANGE GERRIT ,  BACHHOFER HARALD ,  FRANOSCH MARTIN ,  SCHAEFER HERBERT

    IPC: H01L21/8242 ,  H01L27/108

    CPC classification number: H01L27/1085 ,  H01L27/10805

    Abstract: (57) Abstract The invention relates to a DRAM storage capacitor, comprising a dielectric made of silicon nitride and at least two electrodes placed opposite to each other above the dielectric. A material with higher tunnel barrier ( phi beta ) between the Fermi level (F) of the material and the conduction band (L) of the dielectric is used for the electrodes. For said purpose, the appropriate materials are metals such a platinum, tungsten and iridium or silicide. (57) Zusammenfassung Die Erfindung betrifft einen Speicherkondensator für einen DRAM, mit einem aus Siliziumnitrid bestehenden Dielektrikum und mit wenigstens zwei, über das Dielektrikum einander gegenüberliegenden Elektroden. Für die Elektroden wird ein Material mit hoher Tunnelbarriere ( phi beta ) zwischen Fermi-Niveau (F) des Materials und Leitungsband (L) des Dielektrikums verwendet. Geeignete Materialien sind hierfür Metalle wie Platin, Wolfram und Iridium oder Silizide.

    Abstract translation: 本发明涉及一种存储电容器用于DRAM，包括由氮化硅的电介质构成的组，和具有至少两个电极在所述电介质彼此相对。 对于使用电介质的材料具有高的隧道势垒（PHI测试版）的材料和导带（L）的费米能级（F）之间的电极。 用于此目的的合适的材料是金属，例如铂，钨，和铱，或硅化物。

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