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    THERMAL ARCHITECTURE FOR SMART GLASSES
    1.
    发明申请
    THERMAL ARCHITECTURE FOR SMART GLASSES 审中-公开

    公开(公告)号：WO2022235883A1

    公开(公告)日：2022-11-10

    申请号：PCT/US2022/027795

    申请日：2022-05-05

    Applicant: SNAP INC.

    Inventor： ASHWOOD, Andrea ,  NILLES, Gerald ,  SIMONS, Patrick Timothy McSweeney ,  STEGER, Stephen Andrew ,  YOU, Choonshin

    IPC: H05K7/20 ,  G02B27/01 ,  G02C5/00 ,  G02C5/22

    Abstract: A method of dissipating heat generated by imaging devices and processing devices of a wearable electronic eyewear device includes providing a first heat sink thermally connecting the imaging devices to a frame of the eyewear device to sink heat to the frame and providing a second heat sink thermally connecting the processing devices to respective temples of the eyewear device to sink heat to the respective temples. The first and second heat sinks are thermally insulated from each other to direct the heat to different portions of the eyewear device. The processing devices may include a first co-processor disposed in a first temple connected to a first end of the frame and a second co-processor disposed in a second temple connected to a second end of the frame. The resulting eyewear device spreads the heat from heat generating devices over a larger area to minimize overall heating.

    DISCIPLINING CRYSTALS TO SYNCHRONIZE TIMING OF INDEPENDENT NODES
    2.
    发明申请
    DISCIPLINING CRYSTALS TO SYNCHRONIZE TIMING OF INDEPENDENT NODES 审中-公开

    公开(公告)号：WO2023059489A1

    公开(公告)日：2023-04-13

    申请号：PCT/US2022/044977

    申请日：2022-09-28

    Applicant: SNAP INC.

    Inventor： HEGER, Jason ,  NILLES, Gerald

    IPC: G06F1/12 ,  G06F1/16 ,  G06F1/163 ,  H03F2203/45631 ,  H03F3/191 ,  H03F3/26 ,  H03F3/45179 ,  H03F3/66 ,  H03L7/0995

    Abstract: A circuit includes a first system-on-chip (SoC) driven by a first clock generator and a second SoC driven by a second clock generator where the first clock generator and the second clock generator have independent time bases. The first and second clock generators are synchronized using an RLC circuit external to the first clock generator and the second clock generator that converts an output of the first clock generator into current pulses and injects the current pulses into the second clock generator to pull an output of the second clock generator into synchronization with the output of the first clock generator. The RLC circuit converts a voltage output of the first clock generator into current pulses at the resonant frequency or specific harmonics of the output of the first clock generator. The second clock generator may include a ring oscillator into which the current pulses are injected.

    EYEWEAR SURFACE TEMPERATURE EVALUATION
    3.
    发明申请
    EYEWEAR SURFACE TEMPERATURE EVALUATION 审中-公开

    公开(公告)号：WO2022245587A1

    公开(公告)日：2022-11-24

    申请号：PCT/US2022/028525

    申请日：2022-05-10

    Applicant: SNAP INC.

    Inventor： ASHWOOD, Andrea ,  CHAI, Mingyang ,  NILLES, Gerald ,  ROBERTSON, John James ,  ZAFARULLAHKHAN, Mehmood

    IPC: G02B27/01 ,  G02C11/00 ,  H04N13/239

    Abstract: A method and apparatus for monitoring a surface temperature of eyewear proximate a processor to understand the surface temperature as a function of computer instructions, such as when the computer instructions are modified during software design. A sensor is coupled to the eyewear proximate the processor, such as at a temple of the eyewear including the processor, using one or more layers of tape. A server provides instructions to the processor for execution, such as instructions of an application, which instructions vary the utilization of the processor. A testing device, such as a digital multi-meter, is coupled to the sensor, as well as the server, and displays the surface temperature as a function of the processor utilization. The surface temperature of the eyewear is monitored to ensure the surface temperature does not exceed a temperature threshold.

    EYEWEAR CHARGING CASE USING CHARGE PINS AS COMMUNICATION PATH
    5.
    发明申请
    EYEWEAR CHARGING CASE USING CHARGE PINS AS COMMUNICATION PATH 审中-公开

    公开(公告)号：WO2020046749A1

    公开(公告)日：2020-03-05

    申请号：PCT/US2019/047934

    申请日：2019-08-23

    Applicant: SNAP INC.

    Inventor： ALHAIDERI, Miran ,  BAMBERGER, Alex ,  NILLES, Gerald ,  PATTON, Russell, Douglas ,  THAM, Yu, Jiang

    IPC: H02J7/00

    Abstract: A case for an eyewear device having a conductive interface includes a housing that receives the eyewear device. A multi-purpose interface, supported by the housing, includes at least one contact arranged to couple with the conductive interface of the eyewear device when the housing receives the eyewear device. Circuitry is coupled to the at least one contact and includes a processor that detects a connection of the conductive interface of the eyewear device to the multi-purpose interface of the case. The processor performs a charging process during a charge state of the case in which an electrical charge is provided at the multi-purpose interface of the case to the eyewear device. Data is exchanged with the eyewear device during a communication state of the case.

    REGULATED POWER SOURCES
    6.
    发明申请
    REGULATED POWER SOURCES 审中-公开

    公开(公告)号：WO2020005675A1

    公开(公告)日：2020-01-02

    申请号：PCT/US2019/038115

    申请日：2019-06-20

    Applicant: SNAP INC.

    Inventor： NILLES, Gerald ,  PATTON, Russell, Douglas ,  PEREZ, Raul, Alejandro ,  SIMONS, Patrick, Timothy Mcsweeney

    IPC: H02J7/00 ,  G02C11/00 ,  H01M10/44

    Abstract: Disclosed herein are regulated power supplies. The power source delivers power to a system load and includes battery units. The power source also includes power flow devices coupled to the battery units that are configured to provide power from the battery units to the system load. Each power flow device corresponds to a respective one of the battery units, and includes a one direction current flow device connected in series with a current regulator between the respective battery unit and the system load.

    DUAL SYSTEM ON A CHIP EYEWEAR
    7.
    发明申请
    DUAL SYSTEM ON A CHIP EYEWEAR 审中-公开

    公开(公告)号：WO2023064108A1

    公开(公告)日：2023-04-20

    申请号：PCT/US2022/045150

    申请日：2022-09-29

    Applicant: SNAP INC.

    Inventor： HEGER, Jason ,  NILLES, Gerald ,  SIMONS, Patrick, Timothy, McSweeney

    IPC: G06F1/16 ,  G06F1/20

    Abstract: Eyewear devices that include two SoCs that share processing workload. Instead of using a single SoC located either on the left or right side of the eyewear devices, the two SoCs have different assigned responsibilities to operate different devices and perform different processes to balance workload. In one example, the eyewear device utilizes a first SoC to operate displays, and it performs three-dimensional graphics and compositing. A second SoC operates first and second color cameras, first and second computer vision (CV) cameras, an operating system (OS), CV algorithms, and visual odometry (VIO), and it performs hand gesture tracking of the user and provides depth from stereo images. This configuration provides organized logistics to efficiently operate various features, and balanced power consumption.

    LOW POWER CAMERA PIPELINE FOR COMPUTER VISION MODE IN AUGMENTED REALITY EYEWEAR
    9.
    发明申请
    LOW POWER CAMERA PIPELINE FOR COMPUTER VISION MODE IN AUGMENTED REALITY EYEWEAR 审中-公开

    公开(公告)号：WO2022072261A1

    公开(公告)日：2022-04-07

    申请号：PCT/US2021/052136

    申请日：2021-09-27

    Applicant: SNAP INC.

    Inventor： DINGO, Bo ,  DOSHI, Chintan ,  KANE, Alexander ,  KONDRATENKO, Anton ,  NILLES, Gerald ,  ROBERTSON, John, James ,  RYUMA, Dmitry ,  KALKGRUBER, Matthias

    IPC: H04N5/232 ,  G02B27/01 ,  G06F1/16 ,  H04N13/239 ,  H04N9/73

    Abstract: An eyewear device having an image processor operable in a camera pipeline for computer vision (CV) and in augmented reality (AR) systems. The image processor is configured to selectively control a plurality of cameras to provide images having a first resolution in the high power AR mode, and to provide the images having a second resolution in the low power CV mode. The first resolution is higher than the second resolution, and the plurality of cameras consume less power in the CV mode than the AR mode. The image processor controls the camera pipeline to process the first resolution, high image quality (IQ) images from the plurality of cameras to operate in the AR mode, and controls the camera pipeline to process the second resolution, lower IQ images from the plurality of cameras to operate in the CV mode. Substantial power is saved by reducing the resolution of the images using downscaling in the cameras themselves in the CV mode.

    WEARABLE DEVICE LOCATION SYSTEMS ARCHITECTURE
    10.
    发明申请
    WEARABLE DEVICE LOCATION SYSTEMS ARCHITECTURE 审中-公开

    公开(公告)号：WO2020243753A1

    公开(公告)日：2020-12-03

    申请号：PCT/US2020/070099

    申请日：2020-05-29

    Applicant: SNAP INC.

    Inventor： THAM, Yu Jiang ,  ROBERTSON, John James ,  NILLES, Gerald ,  HEGER, Jason ,  VADIVELU, Praveen Babu

    IPC: G01S19/14 ,  G01S19/25 ,  G01S19/40 ,  G01S19/39 ,  G01S5/00 ,  H04N1/32 ,  H04N1/00 ,  H04N1/21

    Abstract: Systems, methods, devices, computer readable media, and other various embodiments are described for location management processes in wearable electronic devices. Performance of such devices is improved with reduced time to first fix of location operations in conjunction with low-power operations. In one embodiment, low-power circuitry manages high-speed circuitry and location circuitry to provide location assistance data from the high-speed circuitry to the low-power circuitry automatically on initiation of location fix operations as the high-speed circuitry and location circuitry are booted from low-power states. In some embodiments, the high-speed circuitry is returned to a low-power state prior to completion of a location fix and after capture of content associated with initiation of the location fix. In some embodiments, high-speed circuitry is booted after completion of a location fix to update location data associated with content.

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