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    MULTI-PURPOSE CAMERAS FOR AUGMENTED REALITY AND COMPUTER VISION APPLICATIONS
    1.
    发明申请
    MULTI-PURPOSE CAMERAS FOR AUGMENTED REALITY AND COMPUTER VISION APPLICATIONS 审中-公开

    公开(公告)号：WO2022072097A1

    公开(公告)日：2022-04-07

    申请号：PCT/US2021/048123

    申请日：2021-08-29

    Applicant: SNAP INC.

    Inventor： DING, Bo ,  DOSHI, Chintan ,  KANE, Alexander ,  ROBERTSON, John James ,  RYUMA, Dmitry

    IPC: H04N13/239 ,  H04N13/296 ,  H04N5/232

    Abstract: Eyewear having an image signal processor (ISP) dynamically operable in a camera pipeline for augmented reality (AR) and computer vision (CV) systems. Multi-purpose cameras are used for simultaneous image capture and CV on wearable AR devices. The cameras are coupled to a frame and configured to generate images, wherein the cameras and the ISP are configured to operate in a first AR mode and capture images having a first resolution suitable for use in AR, and are configured to operate in a second CV mode to provide the images having a second resolution suitable for use in CV. The first resolution in the AR mode is higher than the second resolution in the CV mode, and the cameras and the ISP consume less power in the second CV mode than the first AR mode. The cameras and the ISP save significant system power by operating in the low power mode CV mode.

    DUAL SYSTEM ON A CHIP EYEWEAR
    2.
    发明申请
    DUAL SYSTEM ON A CHIP EYEWEAR 审中-公开

    公开(公告)号：WO2023064125A1

    公开(公告)日：2023-04-20

    申请号：PCT/US2022/045395

    申请日：2022-09-30

    Applicant: SNAP INC.

    Inventor： HEGER, Jason ,  NILLES, Gerald ,  RYUMA, Dmitry ,  SIMONS, Patrick Timothy McSweeney ,  WAGNER, Daniel

    IPC: G06F1/16 ,  G06F1/20 ,  G06F1/329 ,  G06F3/01 ,  G02B27/01

    Abstract: Eyewear devices that include two SoCs (602A, 602B) that share processing workload. Instead of using a single SoC located either on the left or right side of the eyewear devices, the two SoCs have different assigned responsibilities to operate different devices and perform different processes to balance workload. In one example, the eyewear device utilizes a first SoC (602A) to operate a first color camera, a second color camera, a first display, and a second display. The first SoC (602A) and a second SoC (602B) are configured to selectively operate a first and second computer vision (CV) camera algorithms. The first SoC (602A) is configured to perform visual odometry (VIO), track hand gestures of the user, and provide depth from stereo images. This configuration provides organized logistics to efficiently operate various features, and balanced power consumption.

    HARDWARE ENCODER FOR STEREO STITCHING
    4.
    发明申请
    HARDWARE ENCODER FOR STEREO STITCHING 审中-公开

    公开(公告)号：WO2022246373A1

    公开(公告)日：2022-11-24

    申请号：PCT/US2022/072284

    申请日：2022-05-12

    Applicant: SNAP INC.

    Inventor： RYUMA, Dmitry ,  ZARE SEISAN, Farid

    IPC: H04N13/161 ,  H04N13/194 ,  H04N13/344

    Abstract: A system to perform stereo stitching of image frames comprises a stereo camera system and a hardware encoder. The hardware encoder receives a left image stream and a right image stream from the stereo camera system simultaneously and processes the left and right image stream to generate a single stitched encoded frame. The apparatus can also comprise a processor and a memory having instructions stored thereon, when executed by the processor, causes the processor to perform operations comprising receiving the left image stream and the right image stream, processing the left and right image streams and generating a single stitched encoded frame.

    LOW POWER CAMERA PIPELINE FOR COMPUTER VISION MODE IN AUGMENTED REALITY EYEWEAR
    5.
    发明申请
    LOW POWER CAMERA PIPELINE FOR COMPUTER VISION MODE IN AUGMENTED REALITY EYEWEAR 审中-公开

    公开(公告)号：WO2022072261A1

    公开(公告)日：2022-04-07

    申请号：PCT/US2021/052136

    申请日：2021-09-27

    Applicant: SNAP INC.

    Inventor： DINGO, Bo ,  DOSHI, Chintan ,  KANE, Alexander ,  KONDRATENKO, Anton ,  NILLES, Gerald ,  ROBERTSON, John, James ,  RYUMA, Dmitry ,  KALKGRUBER, Matthias

    IPC: H04N5/232 ,  G02B27/01 ,  G06F1/16 ,  H04N13/239 ,  H04N9/73

    Abstract: An eyewear device having an image processor operable in a camera pipeline for computer vision (CV) and in augmented reality (AR) systems. The image processor is configured to selectively control a plurality of cameras to provide images having a first resolution in the high power AR mode, and to provide the images having a second resolution in the low power CV mode. The first resolution is higher than the second resolution, and the plurality of cameras consume less power in the CV mode than the AR mode. The image processor controls the camera pipeline to process the first resolution, high image quality (IQ) images from the plurality of cameras to operate in the AR mode, and controls the camera pipeline to process the second resolution, lower IQ images from the plurality of cameras to operate in the CV mode. Substantial power is saved by reducing the resolution of the images using downscaling in the cameras themselves in the CV mode.

    SYNCHRONIZING SYSTEMS ON A CHIP USING A SHARED CLOCK
    6.
    发明申请
    SYNCHRONIZING SYSTEMS ON A CHIP USING A SHARED CLOCK 审中-公开

    公开(公告)号：WO2023059488A1

    公开(公告)日：2023-04-13

    申请号：PCT/US2022/044967

    申请日：2022-09-28

    Applicant: SNAP INC.

    Inventor： AHN, Samuel ,  HEGER, Jason ,  RYUMA, Dmitry

    IPC: G06F1/14 ,  G06F1/12 ,  G06F1/16 ,  G06F3/01 ,  G06F15/173 ,  G06F15/163 ,  G06F1/04 ,  G06F1/163 ,  G06F13/4221 ,  G06F15/17325 ,  G06F2213/0026 ,  G06F3/011

    Abstract: An electronic eyewear device includes first and second systems on a chip (SoCs) (1300, 1310) having independent time bases that are synchronized by generating a common clock signal from a clock generator (1330) of the first SoC (1300) and simultaneously applying the common clock signal to a first counter (1370) of the first SoC (1300) and a second counter (1380) of the second SoC (1310) whereby the first counter and the second counter count clock edges of the common clock. The clock counts are shared through an interface (1320) between the first SoC and the second SoC and compared to each other. When the clock counts are different, a clock count of the first counter (1370) or the second counter (1380) is adjusted to cause the clock counts to match each other. The adjusted clock count is synchronized to the respective clocks of the first and second SoCs (1300,1310), thus synchronizing the first and second SoCs to each other.

    SYNCHRONIZING SYSTEMS-ON-CHIP USING GPIO TIMESTAMPS
    7.
    发明申请
    SYNCHRONIZING SYSTEMS-ON-CHIP USING GPIO TIMESTAMPS 审中-公开

    公开(公告)号：WO2023059474A1

    公开(公告)日：2023-04-13

    申请号：PCT/US2022/044804

    申请日：2022-09-27

    Applicant: SNAP INC.

    Inventor： AHN, Samuel ,  RYUMA, Dmitry ,  ZHUANG, Richard

    IPC: G06F1/14 ,  G02B2027/0178 ,  G02B27/017 ,  G06F1/10 ,  G06F1/12 ,  G06F1/163 ,  G06F13/24 ,  G06F13/4068 ,  G06F2213/0026 ,  G06F2213/0038 ,  H04J3/065

    Abstract: An electronic eyewear device includes first and second systems-on-chip (SoCs) having independent time bases. The first and second SoCs are connected by a shared general purpose input/output (GPIO) connection and an inter-SoC interface. The first and second SoCs are synchronized to each other by the first SoC asserting the shared GPIO connection to the second SoC where assertion of the message to the shared GPIO connection triggers an interrupt request (IRQ) at the second SoC. The first SoC records a first timestamp for assertion of the message to the GPIO connection, and the second SoC records a second timestamp of receipt of the IRQ. The first SoC sends a message including the first timestamp to the second SoC over the inter-SoC interface. The second SoC calculates a clock offset between the first and second SoCs as a difference between the first and second timestamps.

    SYNCHRONIZING SYSTEMS ON A CHIP USING TIME SYNCHRONIZATION MESSAGES
    8.
    发明申请
    SYNCHRONIZING SYSTEMS ON A CHIP USING TIME SYNCHRONIZATION MESSAGES 审中-公开

    公开(公告)号：WO2023059463A1

    公开(公告)日：2023-04-13

    申请号：PCT/US2022/044671

    申请日：2022-09-26

    Applicant: SNAP INC.

    Inventor： AHN, Samuel ,  RYUMA, Dmitry

    IPC: G06F1/14 ,  G06F1/16 ,  G06F1/163 ,  G06F13/405 ,  G06F2213/0038 ,  H04J3/065 ,  H04J3/0682 ,  H04J3/0685

    Abstract: An electronic eyewear device includes first and second systems on a chip (SoCs) having independent time bases and an inter-SoC interface that connects the first and second SoCs. The operations of the first and second SoCs are synchronized by aligning the time bases for the SoCs using a modified PTP technique. The technique includes the second SoC receiving a time synchronization message from the first SoC over the inter-SoC interface, recording a local timestamp of receipt of the time synchronization message, receiving a master timestamp corresponding to a timestamp recorded by the first SoC corresponding to the time of sending the time synchronization message by the first SoC, and calculating a time offset between the local timestamp and the master timestamp. The time bases of the first SoC and second SoC are then aligned using the calculated time offset. To account for transmission delays, multiple time offsets may be averaged.

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