公开(公告)号：JPH02203551A

公开(公告)日：1990-08-13

申请号：JP2259589

申请日：1989-02-02

Applicant: SONY CORP

Inventor： SUGANO YUKIYASU ,  HAMASHIMA TOSHIKI ,  MINEGISHI SHINJI

IPC: H01L21/768

Abstract: PURPOSE:To form multilayer wiring exhibiting stabilized small contact resistance value by using, as a flattened film, an insulating film to which dopant impurity is not added. CONSTITUTION:On a semiconductor substrate 1, a gate electrode 2 is formed, and an interlayer insulating film 3 is deposited. After SOG solution is spin- coated, a flattened insulating film 4 is formed by baking, which film is composed of inorganic SiO2 only and does not contain dopant impurity. Further, a silicon oxide film 5 is deposited, and a contact hole 6 is formed, in which polysilicon 7 is buried. By using, in this manner, the insulating film to which dopant impurity is not added as the flattened film 4, the diffusion of dopant impurity from the flattened film to the polysilicon can be avoided, and a multilayer wiring exhibiting stabilized small contact resistance value can be formed.

公开(公告)号：JPH0265171A

公开(公告)日：1990-03-05

申请号：JP21600788

申请日：1988-08-30

Applicant: SONY CORP

Inventor： HAMASHIMA TOSHIKI ,  SUMI HIROBUMI

IPC: H01L27/14

Abstract: PURPOSE:To form a highly responsive solid-state image sensing element by arranging a layer having an aperture on a photodetector section; applying a coating glass so that the surface forms a recess with respect to the photodetector section and subjecting it to a thermal treatment; and laminating a film whose refractive index is larger than the liquid glass thereby to flatten the surface of the element. CONSTITUTION:After forming a photodetector section 11 on a silicon substrate 10, an SiO2 film 12 is formed. On this film 12 are a glass layer 13 and an aperture 14 arranged. The inner wall of the aperture 14 is sloped as prescribed. Then, a coating glass SOG 15 is applied over the inner wall. At this time, the SOG 15 within the aperture 14 is shaped as a recess at the center due to surface tension. Then, the member thus obtained is annealed to solidify the SOG 15. A film whose refractive index is larger than the SOG 15, e.g., a SIN film 16, is formed on the SOG 15 by a CVD method. Lastly, the SIN film 16 is flattened and a lens section A is formed. Accordingly, by arranging the lens section by a combination of the SOG 15 and a substance whose refractive index is larger than that of the SOG 15, a lens can be formed easily. Further, light beams are converged properly by the photodetector section, thereby increasing the amount of light per picture element and improving the response of the obtained solid-state image sensing device.

公开(公告)号：JPS62195123A

公开(公告)日：1987-08-27

申请号：JP3662386

申请日：1986-02-21

Applicant: SONY CORP

Inventor： HAMASHIMA TOSHIKI

IPC: H01L21/302 ,  H01L21/3065

Abstract: PURPOSE:To improve the manufacturing efficiency while preventing the DC bias from being diminished by any accumulated positive charge by a method wherein a semiconductor wafer is processed by plasma etching and the like by providing a means to discharge any charge accumulated on the surface of semiconductor wafer out of the semiconductor wafer. CONSTITUTION:An insulating film on the backside of a semiconductor wafer 9 is removed to bond a metallic layer 12 thereon. The metallic layer 12 is simultaneously formed on the sides of wafer 9 as the wafer 9 is very thin. The semiconductor wafer 9 with its backside and sides formed of the metallic layer 12 is set on a substrate holder 8 to perform the DC bias sputtering process. As shown by the dotted line, Ar reaching an Al layer 11 flows down into the substrate holder 8 as a part of electrode not to accumulate any positive charge on the Al layer 11 while preventing the sputtering process from being stopped by the accumulated positive charge.

公开(公告)号：JPS62102540A

公开(公告)日：1987-05-13

申请号：JP24188485

申请日：1985-10-29

Applicant: SONY CORP

Inventor： HAMASHIMA TOSHIKI ,  ASANO KATSUAKI

IPC: H01L21/3205

Abstract: PURPOSE:To simplify the manufacturing steps by applying a bias to a substrate side to sputter it, and forming a primary layer or a wiring layer to smoothen steps, thereby sufficiently smoothening the steps. CONSTITUTION:Abrupt steps 2 are formed on a semiconductor substrate 1. Then, a damage preventing film 3 is coated by depositing by sputtering without applying a bias. Then, a bias is also applied to the substrate side in addition to the normal sputter depositing to simultaneously advance depositing and etching. In this case, a bias sputtered film 4 is deposited integrally with the film 3. This film 4 can increase the curvature of the corner 4a or can smoothen the steps. Then, a necessary wiring layer 5 is formed.

公开(公告)号：JPS6167225A

公开(公告)日：1986-04-07

申请号：JP18849684

申请日：1984-09-08

Applicant: Sony Corp

Inventor： HAMASHIMA TOSHIKI

IPC: H01L21/027 ,  H01L21/30

CPC classification number: H01L21/30

Abstract: PURPOSE:To prevent a cover from peeling from a semiconductor wafer with an annealing treatment after a pattern formation by giving an exposure treatment to a perimeter portion where a semiconductor element of the semiconductor wafer is not formed. CONSTITUTION:An exposure treatment is given to a photoresist film 7 of a positive type with a mask 8. This exposure treatment is given for all the surface of a semiconductor wafer 1 and the light for an exposure is illuminated to a perimeter portion 2 of the semiconductor wafer 1 where a semiconductor element is not formed, and the resist film 7 is planed to sensitize on the perimeter portion 2 where a semiconductor element of the semiconductor wafer 1 is not formed. Therefore, a molybdenum silicide 7 is not only selectively etched on a semiconductor element forming region 4 is but also etched and eliminated perfectly on the perimeter portion 2 by photoetching. According to that, a fear that the molybdenum silicide film 6 is peeled by a stress generated in an annealing treatment is lessened.

Abstract translation: 目的：为了通过对未形成半导体晶片的半导体元件的周边部分进行曝光处理，在图案形成之后，通过退火处理来防止盖从半导体晶片剥离。 构成：对具有掩模8的正型的光致抗蚀剂膜7进行曝光处理。对半导体晶片1的所有表面给出曝光处理，并且将曝光用光照射到半导体晶片1的周边部分2 未形成半导体元件的半导体晶片1，并且在没有形成半导体晶片1的半导体元件的周边部2上使抗蚀膜7平坦化。 因此，不仅在半导体元件形成区域4上选择性地蚀刻硅钼化物7，而且通过光刻在周边部分2上被完全蚀刻和消除。 据此，减少了在退火处理中产生的应力而使硅化钼膜6剥离的担心。

公开(公告)号：JP2578759B2

公开(公告)日：1997-02-05

申请号：JP26339485

申请日：1985-11-22

Applicant: SONY CORP

Inventor： HAMASHIMA TOSHIKI ,  NAKAJIMA HIDEHARU

IPC: H01L29/43 ,  H01L21/28 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/04 ,  H01L27/06 ,  H01L27/088 ,  H01L29/36

公开(公告)号：JPH0354833A

公开(公告)日：1991-03-08

申请号：JP19085389

申请日：1989-07-24

Applicant: SONY CORP

Inventor： HAMASHIMA TOSHIKI

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092

Abstract: PURPOSE:To cut down the manufacturing processes of MIS type transistor by a method wherein the parts corresponding to high concentration impurity regions are implanted with an impurity so as to selectively laser-anneal the said parts. CONSTITUTION:The parts corresponding to high concentration impurity regions are implanted with an impurity to selectively laser-anneal the parts corresponding to the high concentration impurity regions 81, 82, 91, 92 using the masking layers 11, 11a formed on the sidewall of gate electrodes 2, 2a so that a structure provided with an NMOS part 10 and a PMOS part 20 having the high impurity concentration regions 81, 82, 91, 92 as well as the low impurity concentration regions 61, 62, 71, 72 may be erected.

公开(公告)号：JPH0322528A

公开(公告)日：1991-01-30

申请号：JP15808989

申请日：1989-06-20

Applicant: SONY CORP

Inventor： HAMASHIMA TOSHIKI

IPC: H01L21/3205 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/78

Abstract: PURPOSE:To avoid the removal of the ion-implanted regions at the highest concentration even in case the parts beneath contact windows are removed by overetching process by a method wherein the first heattreatment process expanding ion implanted regions to some extent is performed before making contact windows and then the contact windows are made in an insulating film. CONSTITUTION:Before or after the formation of an insulating layer 12 such as SiO2, etc., on the whole surface, the first heat treatment process is performed e.g. in N2 atmosphere at 850 deg.C for 60 minutes meeting the requirements which will not suffice for the activation of ion implanted in the ion-implanted regions 11 but will be effective for expanding the ion-implanted regions 11 deeper than the etching depth (d) in the surface of a semiconductor substrate 21 in case of making contact windows 13. Next, the contact windows 13 are made in the insulating layer 12 corresponding to the respective regions 11 simultaneously forming recessions 25 by the depth (d) on the surface of the semiconductor substrate 21. Next, the whole surface of the insulating layer 12 is coated with semiconductor 14 e.g. polycrystal silicon and etched back so as to be buried in the contact windows 13 e.g. by low pressure CVD process so that the surface of the semiconductor 14 may be almost flush with the surface of the insulating film 12. Next, the semiconductor 14 is doped with an impurity and the second heat treatment is performed. Finally, e.g. metal wirings 26 striding over the buried in semiconductor 14 are formed after a specific pattern.

公开(公告)号：JPS63210271A

公开(公告)日：1988-08-31

申请号：JP4173587

申请日：1987-02-25

Applicant: SONY CORP

Inventor： SUGANO YUKIYASU ,  HAMASHIMA TOSHIKI

IPC: H01L21/285 ,  C23C14/34

Abstract: PURPOSE:To increase the yield of sputtering with Ar ions when a film is formed on the surface of a substrate by DC bias sputtering in a gaseous Ar atmosphere, by controlling the pressure of the gaseous Ar. CONSTITUTION:When a thin film of the substance of a target 1 is formed on the surface of a semiconductor substrate 3 by DC bias sputtering in gaseous Ar as atmospheric gas, the gaseous Ar is ionized by glow discharge caused between the target 1 and a shielding plate as a counter electrode 2 and the target 1 is sputtered as fine particles to form the thin film on the surface of the substrate 3. By reducing the pressure of the gaseous Ar as the atmospheric gas, the average free path of Ar ions is made longer than the distance (l) between the target 1 and the substrate 3, the attenuation of the energy of Ar ions due to scattering is prevented and the yield of sputtering of the target with Ar ions is increased.

公开(公告)号：JPS62125628A

公开(公告)日：1987-06-06

申请号：JP26542985

申请日：1985-11-26

Applicant: SONY CORP

Inventor： HAMASHIMA TOSHIKI

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/31 ,  H01L21/76

Abstract: PURPOSE:To suppress an irregularity in a width of grooves by providing steps of forming predetermined recesses on a semiconductor substrate and sputtering a semiconductor material while applying a bias to the substrate to form grooves narrower in width than the recesses in the recesses. CONSTITUTION:Steps of forming predetermined recesses 12 on a semiconductor substrate 11, depositing a semiconductor material 13 in a predetermined thickness on the substrate 11 including the recesses 12 and sputtering while applying a bias voltage to the substrate to form predetermined grooves 14 narrower in width than the recesses are provided. Si 13 is deposited in the thickness several thousands Angstrom on the substrate 11 to avoid a damage due to a bias sputtering in an element forming region to increase controllability of forming the grooves in the recesses 12. An insulator for separating between elements is buried in the groove 14. In case of forming a capacity element, a thin oxide film 15 is formed in the groove 14 as a dielectric. Thus, the grooves having no irregularity can be formed.