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    IMAGE PICKUP PANEL AND IMAGE PICKUP PROCESSING SYSTEM
    1.
    发明申请
    IMAGE PICKUP PANEL AND IMAGE PICKUP PROCESSING SYSTEM 审中-公开
    图像拾取面板和图像拾取处理系统

    公开(公告)号：WO2013089209A3

    公开(公告)日：2013-08-15

    申请号：PCT/JP2012082436

    申请日：2012-12-07

    Applicant: SONY CORP

    Inventor： OOTORII HIIZU ,  SHIROTA NORIHISA ,  TOGASHI HARUO

    IPC: H01L27/146 ,  G01T1/20

    CPC classification number: G01T1/2018 ,  G01T1/2006 ,  G01T1/202 ,  G01T1/2023 ,  H01L27/14636 ,  H01L27/14663

    Abstract: An image pickup panel (1) includes: photodetection sections (10) each including a photodetector (11-1) and a receiver (11-2) which are integrally molded and having solder bumps (12) formed thereon, the photodetector converting received light into a current signal, the. receiver converting the curnent signal into a voltage signal; and a wiring layer (20) including a wiring pattern installed therein and allowing the photodetection sections to be mounted thereon for respective pixels by the solder bumps, the wiring pattern being connected to the photodetection sections.

    Abstract translation: 一种图像拾取面板（1）包括：光电检测部分（10），每个光电检测部分（10）包括一体模制的光电检测器（11-1）和接收器（11-2），并且在其上形成有焊料凸块（12） 成为当前的信号， 接收器将图像信号转换为电压信号; 以及布线层（20），其中安装有布线图案，并且通过焊料凸块使各个像素的光电检测部分安装在其上，布线图案连接到光电检测部分。

    3.
    发明专利
    未知

    公开(公告)号：DE69428818T2

    公开(公告)日：2002-08-08

    申请号：DE69428818

    申请日：1994-03-09

    Applicant: SONY CORP

    Inventor： SHIROTA NORIHISA ,  KATO YASUNOBU ,  OYA NOBORU

    IPC: G06F15/80 ,  G06F7/48

    Abstract: A parallel arithmetic-logical processing device in which arithmetic-logical processing is shared among and executed in a parallel fashion by a plurality of processing elements. The device includes a large-capacity serial access memory 2 for continuous reading/writing of large-scale data, a small-capacity serial access memory 3 for continuous reading/writing of small-scale data and a high-speed general-purpose random access memory 4 for random writing/readout of small-scale data. A central processing unit (CPU) 5 causes the memories to be used or not used depending on the scale of the arithmetic-logical processing. Since the serial access memory 3 or 4 executes continuous data writing and reading, high-speed access may be achieved, so that it can be manufactured inexpensively with a large storage capacity. Consequently, the processing speed in the CPU 5 may be increased, while the parallel arithmetic-logical processing device may be manufactured inexpensively.

    4.
    发明专利
    未知

    公开(公告)号：DE3853449D1

    公开(公告)日：1995-05-04

    申请号：DE3853449

    申请日：1988-06-17

    Applicant: SONY CORP

    Inventor： SHIROTA NORIHISA

    IPC: H03M13/00 ,  H03M13/03 ,  H03M13/15

    Abstract: A decoding method of Reed-Solomon code produces an error polynomial (x) and an error evaluation polynomial (x) by a Euclidean algorithm, whereby a syndrome polynomial S(x) is obtained, the highest degrees of the syndrome polynomial S(x) and of an initial polynomial x , which is determined by the number t of symbols to be corrected, are multiplied, while the degree is incrementally reduced, thereby obtaining polynomials h(x) and g(x) that satisfy the relation: f(x) B(x) + g(x) S(x) = h(x) (where the degree of h(x) is less than the degree of g(x)

    METHOD AND APPARATUS FOR DECODING REED-SOLOMON CODE
    5.
    发明专利
    METHOD AND APPARATUS FOR DECODING REED-SOLOMON CODE 未知

    公开(公告)号：CA1314995C

    公开(公告)日：1993-03-23

    申请号：CA569732

    申请日：1988-06-17

    Applicant: SONY CORP

    Inventor： SHIROTA NORIHISA

    IPC: H03M13/00 ,  H03M13/03 ,  H03M13/15

    Abstract: 27697 A decoding method of Reed-Solomon code produces an error polynomial (x) and an error evaluation polynomial (x) by a Euclidean algorithm, whereby a syndrome polynomial S(x) is obtained, the highest degrees of the syndrome polynomial S(x) and of an initial polynomial x2t, which is determined by the number t of symbols to be corrected, are multiplied, while the degree is incrementally reduced, thereby obtaining polynomials h(x) and g(x) that satisfy the relation: f(x) B(x) + g(x) S(x) = h(x) (where the degree of h(x) is less than the degree of g(x)? t). The polynomial g(x) is set to the error position polynomial (x), and the polynomial H(x) is set to the error evaluation polynomial (x), thereby performing the decoding by real time processing.

    6.
    发明专利
    未知

    公开(公告)号：DE3586291T2

    公开(公告)日：1993-02-25

    申请号：DE3586291

    申请日：1985-04-11

    Applicant: SONY CORP

    Inventor： SHIROTA NORIHISA ,  YAMAZAKI TAKAO ,  IWASE SEIICHIRO

    IPC: G11B20/10 ,  A63F7/02 ,  G11B20/18 ,  H03K5/00 ,  H03K5/13 ,  H04N5/92 ,  H04N5/95 ,  G06F5/06

    Abstract: There is provided a digital time base corrector in which a digital input signal of one block consisting of a continuous data time sequence is converted to a digital signal including data lack intervals or vice versa by a variable delay circuit (11, 51). A signal selecting circuit (12) is divided into N first unit selecting circuits (21, 22, 23, 24) and a second unit selecting circuit (25). M of the output signals of a shift register (R 1 , R 2 , ...) are inputted to the first unit selecting circuits (21, 22, 23, 24), by which one of them is selected. The outputs of the N first unit selecting circuits (21, 22, 23, 24) are supplied to the second unit selecting circuit (25), by which one of them is selected. A pipeline process is performed by inserting a delay circuit (R 21 , R 22 , R 23 , R 2 4) to delay the signal for the time of one clock period into the input/output line of the second unit selecting circuit (25). Further, the selecting signal can be made variable for every one clock and a delay circuit (33,37) is inserted on the output side of a selecting signal forming circuit (13). With this corrector, the influence of the gate delay of the selectors can be reduced and the high speed data process can be performed.

    9.
    发明专利
    未知

    公开(公告)号：FR2481027B1

    公开(公告)日：1986-06-13

    申请号：FR8107715

    申请日：1981-04-16

    Applicant: SONY CORP

    Inventor： HASHIMOTO YOSHITAKA ,  SHIROTA NORIHISA ,  YAMAMOTO KAICHI

    IPC: G11B20/18 ,  H03K13/32 ,  G11B5/02 ,  H04N5/91

    Abstract: A method for processing a digital color video signal formed of 8-bit words, includes the recording steps of converting each 8-bit word into a 10-bit word in accordance with a predetermined mapping function, grouping the 10-bit words into 48 word blocks, adding to each block an identification signal, identification signal check words P1 and Q1, and data check words P2 and Q2, the latter being formed by the equations: where T-1, T-2, . . . T-(n-1), T-n, T1, T2, . . . Tn-1, Tn are distinct, non-zero elements of a Galois field (2m); and includes the reproducing steps of reconverting each of the 10-bit words to its corresponding 8-bit word in accordance with the predetermined mapping function with the reconverted 8-bit words forming a data unit for each 12 words thereof and a data block for each 48 words thereof, detecting whether any of the 8-bit words contain an error by failing to satisfy the mapping function reconversion, determining that each data unit that includes an 8-bit word having an error is erroneous, detecting and correcting any errors in the identification signals by means of the identification signal check words P1 and Q1, determining whether each erroneous data block and data unit is capable of being corrected and concealing each erroneous data unit that is determined to be uncorrectable and correcting errors in the 8-bit words in each erroneous data block and data unit that is determined to be correctable, by means of the data check words P2 and Q2 and parity words, respectively, thereby forming a continuous, composite digital color video signal, and correcting the phase of the color sub-carrier of each data unit of the composite digital color video signal by comparison of a reference signal with the identification signal of the block to which each respective data unit belongs.

    METHOD AND APPARATUS FOR N-TO-M ENCODING
    10.
    发明专利
    METHOD AND APPARATUS FOR N-TO-M ENCODING 未知

    公开(公告)号：CA1193016A

    公开(公告)日：1985-09-03

    申请号：CA400948

    申请日：1982-04-14

    Applicant: SONY CORP

    Inventor： SHIROTA NORIHISA ,  ABE TAKAO

    IPC: H04L25/49 ,  G11B5/09 ,  G11B20/14 ,  H03M7/14 ,  H03M7/20

    Abstract: METHOD AND APPARATUS FOR n-TO-m BIT ENCODING A method and apparatus are provided for encoding successive n-bit information words into successive m-bit code words wherein m > n. Each n-bit information word is assigned with a respective set of m-bit code words. Each set of code words is comprised of either two or four words. The words in each two-word set have zero disparity, and their first bits are of opposite logical sets. In the four-word sets, two words have positive disparity and their first bits are of opposite logical sense, and the other two words have negative disparity and their first bits also are of opposite logical sense. The particular m-bit code word that is selected from the set associated with the n-bit word commences with the same bit as the last bit of the immediately preceding code word, and the selected code word exhibits a disparity that, when combined with the digital sum variation of the preceding encoded code words, reduces the overall digital sum variation toward zero.

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