公开(公告)号：CA999980A

公开(公告)日：1976-11-16

申请号：CA213927

申请日：1974-11-18

Applicant: SONY CORP

Inventor： YAGI HAJIME ,  TSUYUKI TADAHARU ,  KOMA KOTARO ,  MIYAZAWA YOSHIHIRO

IPC: H01L29/73 ,  H01L21/331 ,  H01L23/48 ,  H01L27/00 ,  H01L29/00

Abstract: A bipolar transistor has an emitter, a base, a collector and additional region which is electrically connected to the base region. The additional region is formed parallel to an emitter-base junction to inject minority carriers into the emitter and has a plurality of windows therein where a plurality of ohmic contacts for the emitter are located.

公开(公告)号：DE69111929T2

公开(公告)日：1996-03-28

申请号：DE69111929

申请日：1991-06-28

Applicant: SONY CORP

Inventor： MIYAZAWA YOSHIHIRO ,  MINAMI ERIC ,  MATSUSHITA TAKESHI

IPC: H01L21/336 ,  H01L29/786 ,  H01L29/772

Abstract: The semiconductor device (34) comprising a semiconductor layer (23) forming a source region (25), a drain region (26), a channel region (27) and a lead-out region (28) is arranged on a thin semiconductor film insulator (22). For increasing the breakdown voltage between source and drain, which is smaller than in a device formed in a bulk silicon, due to holes generated by an impact ionization, the lead-out region (28) adjoined to the source region (25) and/or a further lead-out region adjacent to the drain region (26) are provided so as to reach the bottom of the insulator film (22). Excess holes primarily causes by said impact ionization are pulled off and removed very effectively via said lead-out region(s) thus increasing the breakdown voltage.

公开(公告)号：GB2254487A

公开(公告)日：1992-10-07

申请号：GB9206123

申请日：1992-03-20

Applicant: SONY CORP

Inventor： HASHIMOTO MAKOTO ,  MIYAZAWA YOSHIHIRO ,  MATSUSHITA TAKESHI

IPC: H01L27/11

Abstract: A method of manufacturing a CMOS type SRAM, comprises the steps of forming a first mask layer 13 on a semiconductor layer 11, and patterning the layer 13 to define semiconductor islands A, B where a driver MOS transistor and a load MOS transistor are formable with an isolation region 18 therebetween; forming a second mask layer 15 and patterning it to overlap the region in which one of the transistors is to be formed; but not to overlap the isolating region between the transistors; masking, with a resist film 17, the region in which the other of the transistors is to be formed; and etching the layer 13 while it is masked by the resist film 17 and the layer 15; and etching the semiconductor layer 11 while it is masked by the layer 13, thereby forming mutually isolated semiconductor islands A and B where the transistors are formed.

公开(公告)号：DE69122043T2

公开(公告)日：1997-04-10

申请号：DE69122043

申请日：1991-11-21

Applicant: SONY CORP

Inventor： MIYAZAWA YOSHIHIRO

IPC: H01L21/336 ,  H01L21/337 ,  H01L29/786 ,  H01L29/772 ,  H01L21/331

Abstract: A thin film field effect transistor manufactured using a cladding technique wherein parasitic capacities of the source (24) and drain (12, 15) with respect to the ground are low and a substrate biasing effect is low. The vertical channel field effect transistor comprises a substrate (10), an insulating layer (16) formed on the substrate, and a semiconductor layer formed on the substrate in the insulating layer. The semiconductor layer has one of a source (19) and a drain (12) and an electrode (24, 15) for the one of the source and drain formed at a lower portion thereof while the other of the source and drain and another electrode for the other of the source and drain are formed at an upper portion of the semiconductor layer. The semiconductor layer further has a groove (20) formed therein, and a gate electrode (25) formed in the groove to fill up the same. Several processes of manufacturing such vertical channel field effect transistor are also disclosed.

公开(公告)号：GB2254487B

公开(公告)日：1995-06-21

申请号：GB9206123

申请日：1992-03-20

Applicant: SONY CORP

Inventor： HASHIMOTO MAKOTO ,  MIYAZAWA YOSHIHIRO ,  MATSUSHITA TAKESHI

IPC: H01L27/11

Abstract: A method for manufacture of a full CMOS type SRAM, comprising the steps of forming a first mask layer on a semiconductor layer, and patterning the first mask layer by photolithography to form semiconductor island layers where a driver MOS transistor and a load MOS transistor are formable with a slight space therebetween; forming a second mask layer on the semiconductor layer, and patterning the second mask layer by photolithography in such a manner as to overlap the region with one of the driver and load MOS transistors, but not to overlap the isolating region between the transistors; masking, with a resist film, the region with the other of the driver and load MOS transistors, and etching the first mask layer while masking the same with the resist film and the second mask layer; and etching the semiconductor layer while masking the same with the first mask layer, thereby forming mutually isolated semiconductor island layers where the driver and load MOS transistors are formed respectively. According to this method, the width of each transistor and the space between the transistors can be minimized to consequently achieve an enhanced integration density.

公开(公告)号：DE69122043D1

公开(公告)日：1996-10-17

申请号：DE69122043

申请日：1991-11-21

Applicant: SONY CORP

Inventor： MIYAZAWA YOSHIHIRO

IPC: H01L21/336 ,  H01L21/337 ,  H01L29/786 ,  H01L29/772 ,  H01L21/331

Abstract: A thin film field effect transistor manufactured using a cladding technique wherein parasitic capacities of the source (24) and drain (12, 15) with respect to the ground are low and a substrate biasing effect is low. The vertical channel field effect transistor comprises a substrate (10), an insulating layer (16) formed on the substrate, and a semiconductor layer formed on the substrate in the insulating layer. The semiconductor layer has one of a source (19) and a drain (12) and an electrode (24, 15) for the one of the source and drain formed at a lower portion thereof while the other of the source and drain and another electrode for the other of the source and drain are formed at an upper portion of the semiconductor layer. The semiconductor layer further has a groove (20) formed therein, and a gate electrode (25) formed in the groove to fill up the same. Several processes of manufacturing such vertical channel field effect transistor are also disclosed.

公开(公告)号：DE69111929D1

公开(公告)日：1995-09-14

申请号：DE69111929

申请日：1991-06-28

Applicant: SONY CORP

Inventor： MIYAZAWA YOSHIHIRO ,  MINAMI ERIC ,  MATSUSHITA TAKESHI

IPC: H01L21/336 ,  H01L29/786 ,  H01L29/772

Abstract: The semiconductor device (34) comprising a semiconductor layer (23) forming a source region (25), a drain region (26), a channel region (27) and a lead-out region (28) is arranged on a thin semiconductor film insulator (22). For increasing the breakdown voltage between source and drain, which is smaller than in a device formed in a bulk silicon, due to holes generated by an impact ionization, the lead-out region (28) adjoined to the source region (25) and/or a further lead-out region adjacent to the drain region (26) are provided so as to reach the bottom of the insulator film (22). Excess holes primarily causes by said impact ionization are pulled off and removed very effectively via said lead-out region(s) thus increasing the breakdown voltage.

公开(公告)号：GB2263018B

公开(公告)日：1995-06-21

申请号：GB9301223

申请日：1992-03-20

Applicant: SONY CORP

Inventor： HASHIMOTO MAKOTO ,  MIYAZAWA YOSHIHIRO ,  MATSUSHITA TAKESHI

IPC: H01L27/11

公开(公告)号：GB2263018A

公开(公告)日：1993-07-07

申请号：GB9301223

申请日：1992-03-20

Applicant: SONY CORP

Inventor： HASHIMOTO MAKOTO ,  MIYAZAWA YOSHIHIRO ,  MATSUSHITA TAKESHI

IPC: H01L27/11

Abstract: A static random access memory comprises a semiconductor device wherein a conductive layer (33) is separated from a semiconductor layer (35), which has semiconductor elements (35a, 35b) formed therein, by an insulator film (34). The conductive layer (33) is connected to the semiconductor elements (35a, 35b) via contact holes (36) in the insulator film (34), thereby forming a wiring arrangement. The wiring layer extends over the entire surface and provides a low resistance power supply wiring to the memory cells.

公开(公告)号：DE4209364A1

公开(公告)日：1992-10-22

申请号：DE4209364

申请日：1992-03-23

Applicant: SONY CORP

Inventor： HASHIMOTO MAKOTO ,  MIYAZAWA YOSHIHIRO ,  MATSUSHITA TAKESHI

IPC: H01L27/11

Abstract: A method for manufacture of a full CMOS type SRAM, comprising the steps of forming a first mask layer on a semiconductor layer, and patterning the first mask layer by photolithography to form semiconductor island layers where a driver MOS transistor and a load MOS transistor are formable with a slight space therebetween; forming a second mask layer on the semiconductor layer, and patterning the second mask layer by photolithography in such a manner as to overlap the region with one of the driver and load MOS transistors, but not to overlap the isolating region between the transistors; masking, with a resist film, the region with the other of the driver and load MOS transistors, and etching the first mask layer while masking the same with the resist film and the second mask layer; and etching the semiconductor layer while masking the same with the first mask layer, thereby forming mutually isolated semiconductor island layers where the driver and load MOS transistors are formed respectively. According to this method, the width of each transistor and the space between the transistors can be minimized to consequently achieve an enhanced integration density.