公开(公告)号：CA2306002A1

公开(公告)日：2000-10-26

申请号：CA2306002

申请日：2000-04-18

Applicant: SONY CORP

Inventor： HAYASHI YUTAKA ,  KOBAYASHI TOSHIO ,  MUKAI MIKIO

IPC: H01L27/10 ,  G11C11/405 ,  G11C11/407 ,  H01L27/085

Abstract: A semiconductor memory cell comprising a first transistor for readout, a second transistor for switching, and having a first region, a second region formed in a surface region of the first region, a third region formed in a surface region of the second region, a fourth region formed in a surface region of the first region and spaced from the second region, a fifth region formed in a surface region of the fourth region, and a gate region, wherein when the semiconductor memory cell is cut with a first imaginary perpendicular plane which is perpendicular to the extending direction of the gate region and passes through the center of the gate region, the second region and the fourth region in the vicinity of the gate region are nearly symmetrical with respect to a second imaginary perpendicular plane which is in parallel with the extending direction of the gate region and passes through the center of the gate region.

公开(公告)号：DE69827692D1

公开(公告)日：2004-12-30

申请号：DE69827692

申请日：1998-04-02

Applicant: SONY CORP

Inventor： MUKAI MIKIO ,  HAYASHI YUTAKA

IPC: H01L27/108 ,  G11C11/401 ,  G11C11/403 ,  G11C11/405 ,  H01L21/8242 ,  G11C11/34

Abstract: A semiconductor memory cell comprising (1) a first transistor (TR1) of a first conductivity type for read-out having source/drain regions composed of a surface region of a third region (SC3) and a second region (SC2) and a channel forming region (CH1) composed of a surface region of a first region (SC1), (2) a second transistor (TR2) of a second conductivity type for write-in having source/drain regions composed of the first region (SC1) and a fourth region (SC4) and a channel forming region (CH2) composed of a surface region of the third region (SC3), and (3) a junction-field-effect transistor (TR3) of a first conductivity type for current control having gate regions composed of the fourth region (SC4) and a portion of the first region (SC1) facing the fourth region (SC4), a channel region (CH3) composed of the third region (SC3) sandwiched by the fourth region (SC4) and the first region (SC1) and source/drain regions composed of the third region (SC3).

公开(公告)号：MY129513A

公开(公告)日：2007-04-30

申请号：MYPI20000149

申请日：2000-01-18

Applicant: SONY CORP

Inventor： MUKAI MIKIO ,  HAYASHI YUTAKA

IPC: H01L27/10 ,  H01L27/108 ,  H01L21/8242 ,  H01L27/12 ,  H01L29/772 ,  H01L29/861 ,  H01L29/88 ,  H01L29/94

Abstract: A MEMORY CELL WITH A STORED CHARGE ON ITS GATE COMPRISING: (A) A CHANNEL FORMING REGION (15), (B) A FIRST GATE (13) FORMED ON AN INSULATION LAYER (12) FORMED ON THE SURFACE OF THE CHANNEL FORMING REGION (15), THE FIRST GATE (13) AND THE CHANNEL FORMING REGION (15) FACING EACH OTHER THROUGH THE INSULATING LAYER (18), (C) A SECOND GATE (19) CAPACITIVELY COUPLED WITH THE FIRST GATE, (D) SOURCE/DRAIN REGIONS (16, 17) FORMED IN CONTACT WITH THE CHANNEL FORMING REGION (15), ONE SOURCE/DRAIN REGION (16, 17) BEING SPACED FROM THE OTHER, (E) A FIRST NON-LINEAR RESISTANCE ELEMENT (30) HAVING TWO ENDS, ONE END BEING CONNECTED TO THE FIRST GATE (13), AND (F) A SECOND NON-LINEAR RESISTANCE ELEMENT (33) COMPOSED OF THE FIRST GATE (13), THE INSULATION LAYER (18) AND EITHER THE CHANNEL-FORMING REGION (15) AND AT LEAST ONE OF THE SOURCE/DRAIN REGIONS (16, 17). (FIG. 1A)

公开(公告)号：DE69124476D1

公开(公告)日：1997-03-13

申请号：DE69124476

申请日：1991-10-30

Applicant: SONY CORP

Inventor： MUKAI MIKIO ,  OCHIAI AKIHIKO

IPC: H01L39/22 ,  H01L27/10 ,  H01L29/43 ,  H01L39/24

Abstract: A high speed switching electron device having a semiconductor channel portion (14), superconductive source and drain portions (15,13) formed on upper and lower surfaces of the semiconductor channel portion (14), and a gate electrode (17,19;18,20) formed on a side surface of the channel portion (14) through an insulating film (16). The superconductor switching operation can be controlled satisfactorily and this high speed switching electron device can be densified and highly integrated. Based on similar principles, a superconductor transistor, a high speed memory device, a resonance tunnel effect diode and a resonance tunnel effect transistor are also disclosed.

公开(公告)号：MY130082A

公开(公告)日：2007-05-31

申请号：MYPI9801469

申请日：1998-04-02

Applicant: SONY CORP

Inventor： MUKAI MIKIO ,  HAYASHI YUTAKA

IPC: G11C11/401 ,  H01L27/108 ,  G11C11/403 ,  H01L29/76 ,  G11C11/405 ,  H01L21/8242

Abstract: A SEMICONDUCTOR MEMORY CELL COMPRISING (1) A FIRST TRANSISTOR OF A FIRST CONDUCTIVITY TYPE FOR READ OUT HAVING SOURCE/DRAIN REGIONS COMPOSED OF A SURFACE REGION OF A THIRD REGION AND A SECOND REGION AND A CHANNEL FORMING REGION COMPOSED OF A SURFACE REGION OF A FIRST REGION, (2) A SECOND TRANSISTOR OF A SECOND CONDUCTIVITY TYPE FOR WRITE - IN HAVING SOURCE /DRAIN REGIONS COMPOSED OF THE FIRST REGION AND A FOURTH REGION AND A CHANNEL FORMING REGION COMPOSED OF A SURFACE REGION OF THE THIRD REGION, AND (3) A JUNCTION - FIELD- EFFECT TRANSISTOR OF A FIRST CONDUCTIVITY TYPE FOR CURRENT CONTROL HAVING GATE REGIONS COMPOSED OF THE FOURTH REGION A PORTION OF THE FIRST REGION FACING THE FOURTH REGION, A CHANNEL REGION COMPOSED OF THE THIRD REGION SANDWICHED BY THE FOURTH REGION AND THE FIRST REGION AND SOURCE/ DRAIN REGIONS COMPOSED OF THE THIRD REGION.(FIG. 2)

公开(公告)号：DE69827692T2

公开(公告)日：2005-11-24

申请号：DE69827692

申请日：1998-04-02

Applicant: SONY CORP

Inventor： MUKAI MIKIO ,  HAYASHI YUTAKA

IPC: H01L27/108 ,  G11C11/401 ,  G11C11/403 ,  G11C11/405 ,  H01L21/8242 ,  G11C11/34

Abstract: A semiconductor memory cell comprising (1) a first transistor (TR1) of a first conductivity type for read-out having source/drain regions composed of a surface region of a third region (SC3) and a second region (SC2) and a channel forming region (CH1) composed of a surface region of a first region (SC1), (2) a second transistor (TR2) of a second conductivity type for write-in having source/drain regions composed of the first region (SC1) and a fourth region (SC4) and a channel forming region (CH2) composed of a surface region of the third region (SC3), and (3) a junction-field-effect transistor (TR3) of a first conductivity type for current control having gate regions composed of the fourth region (SC4) and a portion of the first region (SC1) facing the fourth region (SC4), a channel region (CH3) composed of the third region (SC3) sandwiched by the fourth region (SC4) and the first region (SC1) and source/drain regions composed of the third region (SC3).

公开(公告)号：DE69124476T2

公开(公告)日：1997-08-14

申请号：DE69124476

申请日：1991-10-30

Applicant: SONY CORP

Inventor： MUKAI MIKIO ,  OCHIAI AKIHIKO

IPC: H01L39/22 ,  H01L27/10 ,  H01L29/43 ,  H01L39/24

Abstract: A high speed switching electron device having a semiconductor channel portion (14), superconductive source and drain portions (15,13) formed on upper and lower surfaces of the semiconductor channel portion (14), and a gate electrode (17,19;18,20) formed on a side surface of the channel portion (14) through an insulating film (16). The superconductor switching operation can be controlled satisfactorily and this high speed switching electron device can be densified and highly integrated. Based on similar principles, a superconductor transistor, a high speed memory device, a resonance tunnel effect diode and a resonance tunnel effect transistor are also disclosed.

公开(公告)号：JP2001024067A

公开(公告)日：2001-01-26

申请号：JP12404199

申请日：1999-04-30

Applicant: SONY CORP

Inventor： MUKAI MIKIO ,  KOBAYASHI TOSHIO ,  HAYASHI YUTAKA

IPC: H01L27/108 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor memory cell which can make a wiring structure very thin and can simplify the structure. SOLUTION: The semiconductor memory cell includes a first reading transistor TR2, a second switching transistor TR2 and junction type transistor JF1 for current control. The cell has first to fourth regions and an impurity- contained layer SC4A provided on the fourth region SC4. Source/drain regions of the transistor TR1 is made up of a surface zone of the first region SC1 and the fourth region SC4, a channel formation region CH1 is made up of a surface zone of the second region SC2 sandwiched by the surface zone of the first region SC1 and the fourth region SC4, source/drain regions of the transistor TR2 are made up of the surface zone of the second region SC2 and the third region SC3, a channel formation region CH2 is made up of the surface zone of the first region SC1, and a gate region of the junction type transistor is made up of the third and second regions SC3 and SC2.

公开(公告)号：JP2000349171A

公开(公告)日：2000-12-15

申请号：JP15852199

申请日：1999-06-04

Applicant: SONY CORP

Inventor： MUKAI MIKIO ,  KOBAYASHI TOSHIO ,  HAYASHI YUTAKA

IPC: H01L21/8238 ,  H01L21/8242 ,  H01L27/092 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor memory cell which does not require a capacitor of large capacity that a conventional DRAM needs can be elongated enough in a data holding time. SOLUTION: A semiconductor memory cell is composed of a first conductivity-type read-only first transistor TR1 equipped with a source/drain region, a channel forming region CH1, and a gate region G1, a second conductivity-type switching second transistor TR2 equipped with a source/drain region, a channel forming region CH2, and a gate region G2, a junction-type transistor JF1, and an auxiliary capacitor C. One of the source/drain regions of the first transistor TR1 is corresponding to the channel forming region CH2 of the second transistor TR2 and also corresponding to one of the source/drain regions of the junction-type transistor JF1, one of the source/drain regions of the second conductivity-type switching second transistor TR2 is corresponding to the channel forming region CH1 of the first transistor TR1 and also corresponding to the gate of the junction-type transistor JF1, and the auxiliary capacitor C is connected to the channel forming region CH1 of the first transistor TR1.

公开(公告)号：JP2000311954A

公开(公告)日：2000-11-07

申请号：JP11832699

申请日：1999-04-26

Applicant: SONY CORP

Inventor： MUKAI MIKIO ,  KOBAYASHI TOSHIO ,  HAYASHI YUTAKA

IPC: H01L27/108 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor memory cell, wherein two transistors are joined into one body with high flexibility in design or manufacturing. SOLUTION: A semiconductor memory cell is, comprising a first transistor TR1 for reading and a second transistor TR2 for switching, provided with a first region SC1, second region SC2, third region SC3, fourth region SC4, and fifth region SC5 as well as a gate region G. A source/drain regions and channel formation region CH1 of the first transistor TR1 comprise the second region SC2/fourth region SC4 and the surface region of the first region SC1, while the source/drain region and channel formation region CH2 of the second transistor TR2 comprise the surface region of the first region/that of the third region and second region. When a semiconductor memory cell is cut at a first virtual vertical plane PL1, the second region SC2 and the fourth region SC4 near the gate region G are symmetric about a second virtual vertical plane PL2.