公开(公告)号：DE60332017D1

公开(公告)日：2010-05-20

申请号：DE60332017

申请日：2003-06-11

Applicant: SONY CORP

Inventor： ABE HITOSHI ,  ORII TOSHIHIKO ,  AKIMOTO OSAMU ,  MOCHIDA TOSHIHIKO ,  NAKAYAMA SHODAI

IPC: G02F1/1368 ,  G02F1/1362 ,  H01L21/77 ,  H01L27/04 ,  H01L27/12 ,  H01L27/13

Abstract: Disclosed is a semiconductor device capable of realizing a reduction in the area of each pixel without degrading noise resistance. A switching transistor (13) and a signal accumulation capacitor (15) are formed on a semiconductor substrate (base semiconductor region) (11) of a first conduction type, on the basis of each unit region for constituting a pixel Px. The switching transistor (13) has a structure in which a source region (13S) and a drain region (13D) of a second conduction type are formed on the semiconductor substrate (11), and a gate electrode (13G) is formed on the region between the source region (13S) and the drain region (13D), with an insulating layer (12a) therebetween. The signal accumulation capacitor (15) has a structure in which high-concentration semiconductor regions (15D) and (15S) of the first conduction type are formed on the semiconductor substrate (11), and an electrode (15G) is formed on the region between the semiconductor regions (15D) and (15S), with an insulating layer (12b) therebetween. A structure may be adopted in which a bias semiconductor region (17) is not provided, and the semiconductor regions (15D) and (15S) are made to serve also as the bias semiconductor region.

公开(公告)号：AU2003242279B2

公开(公告)日：2008-10-02

申请号：AU2003242279

申请日：2003-06-11

Applicant: SONY CORP

Inventor： ABE HITOSHI ,  ORII TOSHIHIKO ,  NAKAYAMA SHODAI ,  AKIMOTO OSAMU ,  MOCHIDA TOSHIHIKO

IPC: G02F1/1368 ,  G02F1/1362 ,  H01L21/77 ,  H01L27/12 ,  H01L27/13

Abstract: Disclosed is a semiconductor device capable of realizing a reduction in the area of each pixel without degrading noise resistance. A switching transistor (13) and a signal accumulation capacitor (15) are formed on a semiconductor substrate (base semiconductor region) (11) of a first conduction type, on the basis of each unit region for constituting a pixel Px. The switching transistor (13) has a structure in which a source region (13S) and a drain region (13D) of a second conduction type are formed on the semiconductor substrate (11), and a gate electrode (13G) is formed on the region between the source region (13S) and the drain region (13D), with an insulating layer (12a) therebetween. The signal accumulation capacitor (15) has a structure in which high-concentration semiconductor regions (15D) and (15S) of the first conduction type are formed on the semiconductor substrate (11), and an electrode (15G) is formed on the region between the semiconductor regions (15D) and (15S), with an insulating layer (12b) therebetween. A structure may be adopted in which a bias semiconductor region (17) is not provided, and the semiconductor regions (15D) and (15S) are made to serve also as the bias semiconductor region.

公开(公告)号：AU2003242279A1

公开(公告)日：2003-12-22

申请号：AU2003242279

申请日：2003-06-11

Applicant: SONY CORP

Inventor： NAKAYAMA SHODAI ,  MOCHIDA TOSHIKO ,  AKIMOTO OSAMU ,  ORU TOSHIKIKO ,  ABE HITOSHI

IPC: G02F1/1362 ,  G02F1/1368 ,  H01L21/77 ,  H01L27/12 ,  H01L27/13

Abstract: Disclosed is a semiconductor device capable of realizing a reduction in the area of each pixel without degrading noise resistance. A switching transistor (13) and a signal accumulation capacitor (15) are formed on a semiconductor substrate (base semiconductor region) (11) of a first conduction type, on the basis of each unit region for constituting a pixel Px. The switching transistor (13) has a structure in which a source region (13S) and a drain region (13D) of a second conduction type are formed on the semiconductor substrate (11), and a gate electrode (13G) is formed on the region between the source region (13S) and the drain region (13D), with an insulating layer (12a) therebetween. The signal accumulation capacitor (15) has a structure in which high-concentration semiconductor regions (15D) and (15S) of the first conduction type are formed on the semiconductor substrate (11), and an electrode (15G) is formed on the region between the semiconductor regions (15D) and (15S), with an insulating layer (12b) therebetween. A structure may be adopted in which a bias semiconductor region (17) is not provided, and the semiconductor regions (15D) and (15S) are made to serve also as the bias semiconductor region.

公开(公告)号：EP1513005A4

公开(公告)日：2007-02-14

申请号：EP03733360

申请日：2003-06-11

Applicant: SONY CORP

Inventor： ABE HITOSHI ,  ORII TOSHIHIKO ,  AKIMOTO OSAMU ,  MOCHIDA TOSHIHIKO ,  NAKAYAMA SHODAI

IPC: G02F1/1362 ,  G02F1/1368 ,  H01L21/77 ,  H01L27/04 ,  H01L27/12 ,  H01L27/13

CPC classification number: G02F1/1368 ,  G02F1/136213 ,  G02F1/136277 ,  G02F2203/02 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/13

Abstract: Disclosed is a semiconductor device capable of realizing a reduction in the area of each pixel without degrading noise resistance. A switching transistor (13) and a signal accumulation capacitor (15) are formed on a semiconductor substrate (base semiconductor region) (11) of a first conduction type, on the basis of each unit region for constituting a pixel Px. The switching transistor (13) has a structure in which a source region (13S) and a drain region (13D) of a second conduction type are formed on the semiconductor substrate (11), and a gate electrode (13G) is formed on the region between the source region (13S) and the drain region (13D), with an insulating layer (12a) therebetween. The signal accumulation capacitor (15) has a structure in which high-concentration semiconductor regions (15D) and (15S) of the first conduction type are formed on the semiconductor substrate (11), and an electrode (15G) is formed on the region between the semiconductor regions (15D) and (15S), with an insulating layer (12b) therebetween. A structure may be adopted in which a bias semiconductor region (17) is not provided, and the semiconductor regions (15D) and (15S) are made to serve also as the bias semiconductor region.