公开(公告)号：AU2003242279B2

公开(公告)日：2008-10-02

申请号：AU2003242279

申请日：2003-06-11

Applicant: SONY CORP

Inventor： ABE HITOSHI ,  ORII TOSHIHIKO ,  NAKAYAMA SHODAI ,  AKIMOTO OSAMU ,  MOCHIDA TOSHIHIKO

IPC: G02F1/1368 ,  G02F1/1362 ,  H01L21/77 ,  H01L27/12 ,  H01L27/13

Abstract: Disclosed is a semiconductor device capable of realizing a reduction in the area of each pixel without degrading noise resistance. A switching transistor (13) and a signal accumulation capacitor (15) are formed on a semiconductor substrate (base semiconductor region) (11) of a first conduction type, on the basis of each unit region for constituting a pixel Px. The switching transistor (13) has a structure in which a source region (13S) and a drain region (13D) of a second conduction type are formed on the semiconductor substrate (11), and a gate electrode (13G) is formed on the region between the source region (13S) and the drain region (13D), with an insulating layer (12a) therebetween. The signal accumulation capacitor (15) has a structure in which high-concentration semiconductor regions (15D) and (15S) of the first conduction type are formed on the semiconductor substrate (11), and an electrode (15G) is formed on the region between the semiconductor regions (15D) and (15S), with an insulating layer (12b) therebetween. A structure may be adopted in which a bias semiconductor region (17) is not provided, and the semiconductor regions (15D) and (15S) are made to serve also as the bias semiconductor region.

公开(公告)号：DE60208254D1

公开(公告)日：2006-02-02

申请号：DE60208254

申请日：2002-03-11

Applicant: SONY CORP

Inventor： ORII TOSHIHIKO

IPC: H04N5/08 ,  H04N7/035 ,  H04N7/083 ,  H04N7/087 ,  H04N7/088

Abstract: A data slice circuit (30) capable of generating an optimal data slice level and separating data for VBI signals of different specifications, provided with a line detection circuit (33) for detecting any line on which a VBI signal having a CRI signal is superposed and outputting a line detection pulse only during the period and detecting any line on which a VBI signal having a reference signal is superposed and outputting another line detection pulse only during that period, a window pulse generation circuit (34) for outputting pulses changing a period of averaging the VBI signal in accordance with the detection pulses, a data slice reference voltage detection circuit (35) for sampling and holding an average voltage of the clamped VBI signal only while the output pulses are at a high level "H", and a data slice level generation circuit (37) for adding a direct current voltage changed in accordance with the detection pulsed to the output voltage.

公开(公告)号：DE112018004029T5

公开(公告)日：2020-05-28

申请号：DE112018004029

申请日：2018-07-19

Applicant: SONY CORP ,  SONY SEMICONDUCTOR SOLUTIONS CORP

Inventor： TANAKA MASA ,  MOCHIZUKI TAKAHIRO ,  AKIMOTO OSAMU ,  UESHIMA MASAHIRO ,  MOCHIDA TOSHIHIKO ,  ORII TOSHIHIKO ,  ISHIDA TAKAYUKI

IPC: G02F1/13 ,  G02B3/00 ,  G02B5/18 ,  G02B5/32 ,  G02B26/06 ,  G02F1/1343 ,  G03B21/14

Abstract: Der Zweck der vorliegenden Erfindung besteht darin, eine Phasenmodulationsvorrichtung, eine Beleuchtungsvorrichtung und einen Projektor bereitzustellen, bei denen es möglich ist, die Beugungseffizienz eines optischen Phasenmodulationselements zu verbessern. Eine Phasenmodulationsvorrichtung gemäß der vorliegenden Erfindung umfasst zum Beispiel ein optisches Phasenmodulationselement, das eine Vielzahl von Pixeln (10) aufweist und das die Phase von Licht auf Pixelbasis moduliert, wobei die Vielzahl von Pixeln (10) mit wechselseitig unterschiedlichen Pixelpitches p angeordnet ist, um eine Pixelstruktur zu bilden, die das Erzeugen von Beugungsstrahlen hoher Ordnung unterdrückt. Außerdem umfasst die Phasenmodulationsvorrichtung gemäß der vorliegenden Erfindung optische Erfassungssysteme (91, 92, 93, 310), die eine Vielzahl von Beugungsstrahlen hoher Ordnung, die an den einzelnen Pixeln erzeugt werden, erfassen.

公开(公告)号：DE60332017D1

公开(公告)日：2010-05-20

申请号：DE60332017

申请日：2003-06-11

Applicant: SONY CORP

Inventor： ABE HITOSHI ,  ORII TOSHIHIKO ,  AKIMOTO OSAMU ,  MOCHIDA TOSHIHIKO ,  NAKAYAMA SHODAI

IPC: G02F1/1368 ,  G02F1/1362 ,  H01L21/77 ,  H01L27/04 ,  H01L27/12 ,  H01L27/13

Abstract: Disclosed is a semiconductor device capable of realizing a reduction in the area of each pixel without degrading noise resistance. A switching transistor (13) and a signal accumulation capacitor (15) are formed on a semiconductor substrate (base semiconductor region) (11) of a first conduction type, on the basis of each unit region for constituting a pixel Px. The switching transistor (13) has a structure in which a source region (13S) and a drain region (13D) of a second conduction type are formed on the semiconductor substrate (11), and a gate electrode (13G) is formed on the region between the source region (13S) and the drain region (13D), with an insulating layer (12a) therebetween. The signal accumulation capacitor (15) has a structure in which high-concentration semiconductor regions (15D) and (15S) of the first conduction type are formed on the semiconductor substrate (11), and an electrode (15G) is formed on the region between the semiconductor regions (15D) and (15S), with an insulating layer (12b) therebetween. A structure may be adopted in which a bias semiconductor region (17) is not provided, and the semiconductor regions (15D) and (15S) are made to serve also as the bias semiconductor region.

公开(公告)号：DE60208254T2

公开(公告)日：2006-08-24

申请号：DE60208254

申请日：2002-03-11

Applicant: SONY CORP

Inventor： ORII TOSHIHIKO

IPC: H04N5/08 ,  H04N7/035 ,  H04N7/083 ,  H04N7/087 ,  H04N7/088

Abstract: A data slice circuit (30) capable of generating an optimal data slice level and separating data for VBI signals of different specifications, provided with a line detection circuit (33) for detecting any line on which a VBI signal having a CRI signal is superposed and outputting a line detection pulse only during the period and detecting any line on which a VBI signal having a reference signal is superposed and outputting another line detection pulse only during that period, a window pulse generation circuit (34) for outputting pulses changing a period of averaging the VBI signal in accordance with the detection pulses, a data slice reference voltage detection circuit (35) for sampling and holding an average voltage of the clamped VBI signal only while the output pulses are at a high level "H", and a data slice level generation circuit (37) for adding a direct current voltage changed in accordance with the detection pulsed to the output voltage.

公开(公告)号：EP1414005A4

公开(公告)日：2005-01-19

申请号：EP02751828

申请日：2002-08-02

Applicant: SONY CORP

Inventor： ORII TOSHIHIKO ,  AKIMOTO OSAMU ,  ABE HITOSHI ,  ANDO NAOKI

IPC: G01R31/00 ,  G02F1/13 ,  G02F1/1362 ,  G02F1/1368 ,  G09F9/00 ,  G09F9/30 ,  G09G3/20 ,  G09G3/36 ,  G02F1/133 ,  G09G3/00

CPC classification number: G02F1/136259 ,  G02F2001/136254 ,  G09G3/3648

Abstract: A method for inspecting a semiconductor substrate constituting a liquid crystal display by reliably detecting a change in potential due to a failure of a pixel cell driver circuit irrespective of the decreased ratio of the pixel capacitance to the wiring capacitance because of the small size of the display and higher definition. The method comprises a charge retaining step of allowing pixel capacitors connected to pixel switches selected from among all the pixel switches connected to one data line to retain the charge and a detecting step for simultaneously detecting the charge retained by the pixel capacitors at the charge retaining step from the one data line.

Abstract translation: 一种用于测试形成液晶显示装置的半导体衬底的方法，即使当像素电容与布线电容的比例随着尺寸的减小而降低时，也能够精确地检测对应于像素单元驱动电路的缺陷状态的电位变化的方法 或增加液晶显示装置的定义。 该方法包括：电荷保持步骤，用于使与连接到一个数据线的所有像素开关中选择的多个像素开关连接的像素电容保持电荷; 以及检测步骤，用于从所述一条数据线同时检测所述电荷保留步骤中的多个像素电容中保留的电荷。

公开(公告)号：EP1416467A4

公开(公告)日：2006-09-27

申请号：EP02760585

申请日：2002-08-08

Applicant: SONY CORP

Inventor： ORII TOSHIHIKO ,  AKIMOTO OSAMU ,  ABE HITOSHI ,  YOKOKURA TORU

IPC: G02F1/1362 ,  G09G3/36 ,  G02F1/133 ,  G09G3/20

CPC classification number: G09G3/3677 ,  G09G3/3614 ,  G09G3/3648 ,  G09G3/3688 ,  G09G2310/0248 ,  G09G2310/0251 ,  G09G2310/06

Abstract: Two voltages for scanning a scanning line, i.e., AVD1 below a gate breakdown voltage of a switching element and AVD2 over the gate breakdown voltage are selectively used. After the scanning of a scanning line by the AVD1 is started, a data line is precharged. Thereafter, the scanning voltage is changed to the AVD2. At this change, a voltage corresponding to the precharging voltage is generated in a pixel capacitor. Therefore, even if the AVD2 over the gate breakdown voltage is applied to the pixel switch, it is possible to cause a potential difference not exceeding the breakdown voltage between the terminals of the switching element.

Abstract translation: 用于扫描线扫描的电压可以在开关元件的栅极耐受电压和高于栅极耐压的AVD2之间的AVD1之间切换。 在水平消隐期间内，以AVD1开始扫描线的扫描，然后进行数据线的预充电。 此后，将电压切换到AVD2。 由于在这个时间点，像素电容器中产生与预充电电压相对应的电位，所以即使将超过耐受电压的AVD2施加到像素开关，也可以产生不超过耐电压的电位差 在开关元件的端子之间。

公开(公告)号：EP1513005A4

公开(公告)日：2007-02-14

申请号：EP03733360

申请日：2003-06-11

Applicant: SONY CORP

Inventor： ABE HITOSHI ,  ORII TOSHIHIKO ,  AKIMOTO OSAMU ,  MOCHIDA TOSHIHIKO ,  NAKAYAMA SHODAI

IPC: G02F1/1362 ,  G02F1/1368 ,  H01L21/77 ,  H01L27/04 ,  H01L27/12 ,  H01L27/13

CPC classification number: G02F1/1368 ,  G02F1/136213 ,  G02F1/136277 ,  G02F2203/02 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/13

Abstract: Disclosed is a semiconductor device capable of realizing a reduction in the area of each pixel without degrading noise resistance. A switching transistor (13) and a signal accumulation capacitor (15) are formed on a semiconductor substrate (base semiconductor region) (11) of a first conduction type, on the basis of each unit region for constituting a pixel Px. The switching transistor (13) has a structure in which a source region (13S) and a drain region (13D) of a second conduction type are formed on the semiconductor substrate (11), and a gate electrode (13G) is formed on the region between the source region (13S) and the drain region (13D), with an insulating layer (12a) therebetween. The signal accumulation capacitor (15) has a structure in which high-concentration semiconductor regions (15D) and (15S) of the first conduction type are formed on the semiconductor substrate (11), and an electrode (15G) is formed on the region between the semiconductor regions (15D) and (15S), with an insulating layer (12b) therebetween. A structure may be adopted in which a bias semiconductor region (17) is not provided, and the semiconductor regions (15D) and (15S) are made to serve also as the bias semiconductor region.

公开(公告)号：JP2005308796A

公开(公告)日：2005-11-04

申请号：JP2004121741

申请日：2004-04-16

Applicant: Sony Corp ,  ソニー株式会社

Inventor： OKAWA YOSHIRO ,  ORII TOSHIHIKO ,  AKIMOTO OSAMU

IPC: G02F1/1368 ,  G02F1/133 ,  G02F1/1343 ,  G02F1/1362

CPC classification number: G02F1/133512 ,  G02F1/133553 ,  G02F1/136259 ,  G02F1/136277 ,  G02F1/136286 ,  G02F2001/136218 ,  G09G3/3648 ,  G09G2300/0426 ,  G09G2320/0209

Abstract: PROBLEM TO BE SOLVED: To provide a liquid crystal display device whose picture quality is improved by reducing a coupling noise and a jump-in noise with an adjacent wire or an element and which can be treated as a defect-free device by being imparted with redundancy even when a wiring short circuit of a pixel is generated. SOLUTION: Display pixels are arranged on respective intersections of a plurality of vertical signal lines and a plurality of horizontal signal lines. At the same time, shield lines are arranged along the respective vertical and horizontal signal lines. Furthermore, the potential of the shield lines is set to be a value with which the display pixel is displayed in black. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种液晶显示装置，其通过减少与相邻的线或元件的耦合噪声和跳入噪声来改善图像质量，并且可以通过以下方式被视为无缺陷的装置 即使产生像素的布线短路，也赋予冗余。 解决方案：显示像素布置在多条垂直信号线和多条水平信号线的相应交叉点上。 同时，屏蔽线沿相应的垂直和水平信号线布置。 此外，屏蔽线的电位被设定为以黑色显示显示像素的值。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2005055587A

公开(公告)日：2005-03-03

申请号：JP2003284918

申请日：2003-08-01

Applicant: Sony Corp ,  ソニー株式会社

Inventor： ORII TOSHIHIKO

IPC: G02F1/13 ,  G02F1/1343 ,  G03B21/00 ,  G09F9/30 ,  G09F9/35

Abstract: PROBLEM TO BE SOLVED: To miniaturize the size of a semiconductor substrate by improving the layout of pixel cells.
SOLUTION: The respective pixel cells are constituted of pixel switches M 20 to M 23 selected by gate lines, pixel electrodes into which image data is written from data lines D 20 and D 21 through the selected pixel switches, and pixel capacitors CS 20 to CS 23 which are connected to the pixel switches and hold the image data. The pixel cells, one pair of which is arranged symmetrically with a horizontal scanning direction as one unit, are arranged in a matrix form. The boundaries between the pixel capacitors adjacent to each other in a vertical scanning direction are made of the same arrangement in all the pixel cells. Also, the pixel cells, one pair of which are arranged symmetrically with the vertical scanning direction as one unit, are arranged in the matrix form and the data lines D 20 and D 21 connected to the drains D of the transistors constituting the respective pixel switches are wired adjacently in parallel to each other and are always driven at the same timing.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：通过改善像素单元的布局来使半导体衬底的尺寸小型化。 各像素单元由栅极线选择的像素开关M 20〜M 23，通过所选择的像素开关从数据线D20和D21写入图像数据的像素电极以及像素电容器CS 20至CS 23，其连接到像素开关并保持图像数据。 以水平扫描方向对称地配置的一对像素单元作为一个单位排列成矩阵状。 在垂直扫描方向上彼此相邻的像素电容器之间的边界在所有像素单元中由相同的排列构成。 此外，像素单元（其一对以垂直扫描方向对称地排列为一个单位）以矩阵形式布置，并且数据线D20和D21连接到构成各个像素开关的晶体管的漏极D 相互并联连接并且始终以相同的时间驱动。 版权所有（C）2005，JPO＆NCIPI