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公开(公告)号：DE69416554T2
公开(公告)日：1999-08-26
申请号：DE69416554
申请日：1994-08-24
Applicant: SONY CORP
Inventor： OGAWA AKIHIDE , TAKEDA KAZUHIRO , GOSEKI MASAMI
Abstract: In a ring oscillator type VCO in which plural stages of inverter circuits (10) are cascade-connected to each other so as to constitute a positive feedback loop, both of delay amounts for a rising edge and a falling edge of an output signal from the inverter circuit are controlled to have the same delay amount by way of a control signal (Vc). These delay amounts of the rising edge and the falling edge are controllable in such a manner that the duty ratio of an oscillator output signal is not varied. Each stage (10) of the inverter circuit is arranged by three-staged inverters made of load transistors (QL) and driver transistors (QD), and the control voltage (Vc) is applied to the load transistors of the two adjoining inverters among the three-staged inverters.
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公开(公告)号：DE69416554D1
公开(公告)日：1999-03-25
申请号：DE69416554
申请日：1994-08-24
Applicant: SONY CORP
Inventor： OGAWA AKIHIDE , TAKEDA KAZUHIRO , GOSEKI MASAMI
Abstract: In a ring oscillator type VCO in which plural stages of inverter circuits (10) are cascade-connected to each other so as to constitute a positive feedback loop, both of delay amounts for a rising edge and a falling edge of an output signal from the inverter circuit are controlled to have the same delay amount by way of a control signal (Vc). These delay amounts of the rising edge and the falling edge are controllable in such a manner that the duty ratio of an oscillator output signal is not varied. Each stage (10) of the inverter circuit is arranged by three-staged inverters made of load transistors (QL) and driver transistors (QD), and the control voltage (Vc) is applied to the load transistors of the two adjoining inverters among the three-staged inverters.
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公开(公告)号：JPH0746443A
公开(公告)日：1995-02-14
申请号：JP20468493
申请日：1993-07-27
Applicant: SONY CORP
Inventor： OGAWA SHOEI , YAMAGATA YUTAKA , TAKEDA KAZUHIRO , ITO YOSHIHARU
Abstract: PURPOSE:To make the size of the SYNC tip clamping/synchronization separating circuit by a CMOS process small and to reduce the cost. CONSTITUTION:A final output amplifier section 17B of a differential amplifier circuit 17 is made up of a P-channel FETQ16 and a current pulling down a drain terminal of the P-channel FETQ16 is set smaller than a current flowing when the P-channel FETQ16 is turned on. A predetermined voltage is impressed to a noninverting input terminal (+) of the differential amplifier circuit 17 by resistors 18, 19, and an inverting input terminal (-) of the differential amplifier circuit 17 and an output terminal 14 are connected and an input coupling capacitor 5 is interposed between the inverting input terminal (-) and a video signal input terminal 1. Furthermore, a buffer 20 is provided, which extracts a synchronizing signal from the input of the P-channel FET16.
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Patent Agency Ranking
公开(公告)号：JPH05191188A
公开(公告)日：1993-07-30
申请号：JP2054192
申请日：1992-01-08
Applicant: SONY CORP
Inventor： YAMADA TAKAAKI , KUMANO KAZUO , TAKEDA KAZUHIRO
Abstract: PURPOSE:To attain low power consumption by providing a signal compression/ expansion circuit with satisfactory input/output characteristic in a CMOS process. CONSTITUTION:An expanded analog signal So can be obtained by supplying an analog signal Si to a multiplication type D/A converter 22, detecting a signal level by a level detection circuit 23, converting a detection level S1 to digital data Sd of (m) bits by an A/D converter 25, and controlling the multiplication type D/A converter 22 by the digital data Sd.
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公开(公告)号：JP2000151404A
公开(公告)日：2000-05-30
申请号：JP32183198
申请日：1998-11-12
Applicant: SONY CORP
Inventor： TAKEDA KAZUHIRO , TANAKA TAKESHI , MAEKAWA ITARU
Abstract: PROBLEM TO BE SOLVED: To provide a D/A conversion circuit with high precision where a stable voltage output can be acquired independently of a load circuit and to suppress interference among the D/A conversion circuits in the case of employing a plurality of the D/A conversion circuits. SOLUTION: A differential comparator circuit 50 compares a differential output voltage (Vout-Vxout) with a differential reference signal (VA-VB) and controls a count value cnt of an up-down counter 60 according to its comparison signal cmp. A switch S3 of a reference voltage correction 70 is controlled depending on the count value cnt to control a level of a reference voltage V1. A comparator circuit 10 compares the reference voltage V1 with a voltage V2, outputs a comparison signal V3 to control an output current of each of a current source 12 and a current source circuit 22. Then a maximum value of a differential output voltage is independent of a load circuit and kept to a level nearly equal to that of the differential reference signal and then a stable voltage output can be realized.
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公开(公告)号：JPH0766693A
公开(公告)日：1995-03-10
申请号：JP23097293
申请日：1993-08-24
Applicant: SONY CORP
Inventor： OGAWA SHOEI , TAKEDA KAZUHIRO , GOSEKI SHOZO
Abstract: PURPOSE:To control the delay quantities of leading edges and trailing edges of an output waveform without causing variation in duty ratio by applying a control voltage to the load transistors(TR) of two adjacent inverters among three stages of inverters. CONSTITUTION:The inverting circuit of the ring oscillator type VCO is constituted by cascading the three stages of inverters. The p channel MOS TRs of the inverters in the 1st and 2nd stages are both controlled as the load TRs QL and QL with the control voltage VC. The inverter in the 3rd stage is a normal CMOS inverter. Therefore, the rising speed of signals Va and Vb at nodes (a) and (b) when they rise from 0V to a level VCC varies with the values of currents flowing to the load TRs QL because of load capacity. Consequently, the leading edges and trailing edges of the output Vout can be delayed by the same quantity.
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公开(公告)号：JP2013068837A
公开(公告)日：2013-04-18
申请号：JP2011207986
申请日：2011-09-22
Inventor： ANDO NAOKI , TSUKAMOTO KOJI , URAKAWA TAKAMITSU , TAKEDA KAZUHIRO , KAWAGUCHI KEIKO , HOSHIHARA DAIZO , HASHIGAKI KOICHI
CPC classification number: G09G3/3685 , G09G3/3648 , G09G3/3688 , G09G5/18 , G09G2300/0404 , G09G2310/0248
Abstract: PROBLEM TO BE SOLVED: To suppress potential variations in data lines and thereby perform display with less image quality degradation caused by the potential variations.SOLUTION: A short circuit is provided for each of the plurality of pairs of data lines, and allows the pair of data lines to be short-circuited. Before writing of an image signal to a pixel, the pair of data lines is put in a high-impedance state. The short circuit temporarily puts the pair of data lines in a short-circuit state before writing of the image signal to the pixel, to set the potential between the pair of data lines to an intermediate potential between a positive-phase potential and a negative-phase potential, and then releases the short-circuit state to perform writing of the image signal.
Abstract translation: 要解决的问题：为了抑制数据线的潜在变化，从而以较小的由电位变化引起的图像质量劣化进行显示。 解决方案：为多对数据线中的每一条提供短路，并允许数据线对短路。 在向像素写入图像信号之前，将该对数据线置于高阻抗状态。 在将图像信号写入像素之前，短路暂时将该对数据线放置在短路状态，将一对数据线之间的电位设置为正相电位与负电位之间的中间电位， 相位电位，然后释放短路状态以执行图像信号的写入。 版权所有（C）2013，JPO＆INPIT
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公开(公告)号：JP2013068836A
公开(公告)日：2013-04-18
申请号：JP2011207985
申请日：2011-09-22
Inventor： TSUKAMOTO KOJI , TAKEDA KAZUHIRO , URAKAWA TAKAMITSU , ANDO NAOKI , ONO KAZUTOSHI
IPC: G02F1/1368 , G02F1/133 , G09G3/20 , G09G3/36
CPC classification number: G09G3/3413 , G09G3/3614 , G09G2300/0426 , G09G2300/0833 , G09G2300/0838 , G09G2300/0857 , G09G2320/0247
Abstract: PROBLEM TO BE SOLVED: To provide an electro-optical unit and a display that allow an area of a pixel circuit to be reduced.SOLUTION: The electro-optical unit includes: a plurality of pixels provided correspondingly to portions where a plurality of pairs of data lines with two data lines assigned as a pair and a plurality of gate lines intersect with each other. Each of the pixels has an electro-optical device, and a pixel circuit that is connected with the electro-optical device. The pixel circuit has a holding circuit connected with one of the plurality of pairs of data lines and one of the plurality of the gate lines, and a selection circuit connected with an output of the holding circuit and the electro-optical device.
Abstract translation: 要解决的问题：提供允许像素电路的面积减小的电光单元和显示器。 电光单元包括：与分配有两条数据线的多条数据线对和多条栅极线彼此相交的部分相应地设置的多个像素。 每个像素具有电光装置，以及与电光装置连接的像素电路。 像素电路具有与多条数据线之一和多条栅极线之一连接的保持电路，以及与保持电路和电光器件的输出连接的选择电路。 版权所有（C）2013，JPO＆INPIT
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