公开(公告)号：WO2008084085A9

公开(公告)日：2009-09-03

申请号：PCT/EP2008050260

申请日：2008-01-10

Applicant: ST MICROELECTRONICS CROLLES 2 ,  NXP BV ,  MUELLER MARKUS ,  BIDAL GREGORY

Inventor： MUELLER MARKUS ,  BIDAL GREGORY

IPC: H01L21/28

CPC classification number: H01L29/517 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/28105 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

Abstract: The invention concerns a method of forming a field effect transistor comprising a gate (G) formed on an insulating layer, the gate having, in a zone in contact with the insulating layer, a semiconducting central zone (50) and lateral zones (48) in the length of the gate (G), the method comprising forming a gate (G) comprising a portion of insulating layer (32), a portion of semiconducting layer formed over the insulating layer (32), and a portion of mask layer formed over the semiconducting layer; performing an etching of the portion of the mask layer such that only a portion in the centre of the gate (G) remains; and reacting the semiconducting gate with a metal deposited over the gate.

Abstract translation: 本发明涉及一种形成场效应晶体管的方法，该场效应晶体管包括形成在绝缘层上的栅极（G），该栅极在与绝缘层接触的区域内具有半导体中心区域（50）和侧向区域（48） 在栅极（G）的长度上，所述方法包括形成包括绝缘层（32）的一部分的栅极（G），形成在绝缘层（32）上的半导体层的一部分，以及形成的掩模层的一部分 在半导体层上; 对掩模层的部分进行蚀刻，使得只有栅极（G）的中心部分保留; 并使半导电栅极与沉积在栅极上的金属反应。

公开(公告)号：DE602008005557D1

公开(公告)日：2011-04-28

申请号：DE602008005557

申请日：2008-01-10

Applicant: ST MICROELECTRONICS CROLLES 2

Inventor： MUELLER MARKUS ,  BIDAL GREGORY

IPC: H01L21/28

公开(公告)号：DE602008006465D1

公开(公告)日：2011-06-01

申请号：DE602008006465

申请日：2008-09-22

Applicant: NXP BV ,  ST MICROELECTRONICS CROLLES 2

Inventor： CORONEL PHILIPPE ,  DUMONT BENJAMIN ,  POUYDEBASQUE ARNAUD ,  MUELLER MARKUS

IPC: H01L21/335 ,  H01L29/06

公开(公告)号：AT506696T

公开(公告)日：2011-05-15

申请号：AT08804548

申请日：2008-09-22

Applicant: ST MICROELECTRONICS CROLLES 2 ,  NXP BV

Inventor： CORONEL PHILIPPE ,  DUMONT BENJAMIN ,  POUYDEBASQUE ARNAUD ,  MUELLER MARKUS

IPC: H01L21/335 ,  H01L29/06

Abstract: A process for forming a wire portion in an integrated electronic circuit includes epitaxially growing the wire portion on a side surface of a seed layer portion (11, 12). Cross-sectional dimensions of the wire portion correspond to a thickness of the seed layer portion and to a duration of the growing step. The seed layer portion is then selectively removed while the wire portion is retained fixedly on the circuit. Afterwards, heating of the circuit can cause the wire portion becoming rounded in cross-section. The wire portion obtained may be about 10 nanometers in diameter. It may be used for forming a channel of a MOS transistor devoid of short channel effect.