2.
    发明专利
    未知

    公开(公告)号:AT506696T

    公开(公告)日:2011-05-15

    申请号:AT08804548

    申请日:2008-09-22

    Abstract: A process for forming a wire portion in an integrated electronic circuit includes epitaxially growing the wire portion on a side surface of a seed layer portion (11, 12). Cross-sectional dimensions of the wire portion correspond to a thickness of the seed layer portion and to a duration of the growing step. The seed layer portion is then selectively removed while the wire portion is retained fixedly on the circuit. Afterwards, heating of the circuit can cause the wire portion becoming rounded in cross-section. The wire portion obtained may be about 10 nanometers in diameter. It may be used for forming a channel of a MOS transistor devoid of short channel effect.

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