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    FORMING METHOD OF MASK ON INTEGRATED ELECTRONIC CIRCUIT
    1.
    发明专利
    FORMING METHOD OF MASK ON INTEGRATED ELECTRONIC CIRCUIT 审中-公开

    公开(公告)号：JP2006344979A

    公开(公告)日：2006-12-21

    申请号：JP2006160600

    申请日：2006-06-09

    Applicant: ST MICROELECTRONICS CROLLES 2

    Inventor： BUSTOS JESSY ,  THONY PHILIPPE ,  CORONEL PHILIPPE

    IPC: H01L21/027 ,  G03F7/20 ,  H01L21/3205 ,  H01L21/336 ,  H01L29/786

    Abstract: PROBLEM TO BE SOLVED: To easily form a circuit member at an upper position of a cavity buried in a substrate, on the substrate of an integrated electronic circuit. SOLUTION: The upper part of the cavity C formed in the substrate 100 of the integrated electronic circuit is closed, and a hollow E is formed. The hollow E is buried by a material 10 selected so that reflection of a lithography radiation F1 may be weakened. If the radiation is irradiated after a resist layer 3 is laminated on the circuit, a portion positioned at the upper part of the hollow E of the resist layer 3 is exposed to a dosage which is lower than a threshold of development of a resist only by primary flux F1. A portion outside the hollow of the resist layer 3 is exposed to the higher dosage than the threshold, by the primary flux F1 and secondary flux F2 reflected from a surface of the substrate 100. When the resist layer 3 is developed, a mask M2 is obtained only at the upper part of the cavity C. COPYRIGHT: (C)2007,JPO&INPIT

    9.
    发明专利
    未知

    公开(公告)号：FR2911721B1

    公开(公告)日：2009-05-01

    申请号：FR0752776

    申请日：2007-01-19

    Applicant: ST MICROELECTRONICS CROLLES 2

    Inventor： CORONEL PHILIPPE ,  FENOUILLET BERANGER CLAIRE

    IPC: H01L21/84 ,  H01L27/12

    Abstract: The device (1) has an upper region (102) including a MOSFET type semiconductor device i.e. P-channel MOS transistor (106), with a metallic gate (108) and arranged on a semiconductor layer (118). A lower region (104) has a MOSFET type semiconductor device i.e. N-channel MOS transistor (134), arranged on a portion (132b) of another semiconductor layer, where the layers are made of strained silicon. The transistor (134) has a gate (128b) formed by a portion of a metallic layer. The latter semiconductor layer is arranged on an insulating layer (146) stacked on another metallic layer (148). An independent claim is also included for a method of manufacturing a silicon-on-insulator MOSFET device.

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