公开(公告)号：GB2494625A

公开(公告)日：2013-03-20

申请号：GB201115384

申请日：2011-09-06

Applicant: ST MICROELECTRONICS GRENOBLE 2

Inventor： URZI IGNAZIO ANTONINO ,  GRACIANNETTE NICOLAS

IPC: G06F13/16 ,  G06F21/60 ,  G06F21/62

Abstract: A data processing system has a security engine, such as a data scrambler, which processes data transferred to and from a memory. Memory operations are passed to the engine and the memory controller in parallel. The time the operation is passed to the memory controller may be controlled, such that the delay in the engine is less than or equal to the delay in the memory controller. The system may adjust the time based on delay information from the memory controller and the engine. This information may be the latency. The information may be determined from the time between a memory operation being received and the engine being ready to process the data.

公开(公告)号：GB2507124A

公开(公告)日：2014-04-23

申请号：GB201218933

申请日：2012-10-22

Applicant: ST MICROELECTRONICS GRENOBLE 2 ,  ST MICROELECTRONICS SRL

Inventor： MANGANO DANIELE ,  URZI IGNAZIO-ANTONINO ,  GRACIANNETTE NICOLAS

IPC: G06F13/14 ,  H04L47/30 ,  G06F15/78

Abstract: A first device sends data to a second device via a communication path across an interconnect. The second device sends feedback to the first device. The feedback may be the time taken for a request to reach the second device and the response to return to the first device. The feedback may be the amount of data stored in a buffer on the second device. This may be whether the amount of data exceeds a threshold. The first device adjusts the rate at which it outputs data to the second device based on the feedback. It may adjust the bandwidth allocated to the data or the frequency with which it transmits data. The first device may send a request for feedback via a different path to that on which the data is sent.