公开(公告)号：FR3097345A1

公开(公告)日：2020-12-18

申请号：FR1906337

申请日：2019-06-13

Applicant: STMICROELECTRONICS GRAND OUEST SAS ,  ST MICROELECTRONICS GRENOBLE 2

Inventor： PALLARDY LOIC ,  URZI IGNAZIO ANTONINO ,  DURET JEAN-FRANCIS

IPC: G06F13/16

Abstract: Le circuit intégré (CI) comprend une unité de traitement (13) configurée pour démarrer avec un jeu d’instructions de démarrage, puis pour déterminer la taille des instructions d’un programme applicatif (APP) et éventuellement redémarrer sur sa propre initiative, en étant reconfigurée, afin qu’elle exécute les instructions du programme applicatif. Une seule mémoire de démarrage est par conséquent nécessaire. Figure pour l’abrégé : Fig 1

公开(公告)号：GB2495931A

公开(公告)日：2013-05-01

申请号：GB201118412

申请日：2011-10-25

Applicant: ST MICROELECTRONICS GRENOBLE 2 ,  ST MICROELECTRONICS PVT LTD

Inventor： URZI IGNAZIO ANTONINO ,  SHARMA VIVEK MOHAN

IPC: G06F13/38

Abstract: A method for transmitting data on a configurable bus, comprising a number of physical links RD[z], comprises receiving input data on an input bus 10 at one or more of a number of data rates; selecting a number of the physical links on which the data is to be transmitted and a clock frequency at which the data is to be transmitted, based on information relating to the data rate of the input data and the number of links used on the input bus; and driving the physical links to transmit the data. The selection of transmission settings is intended to provide an optimal balance between bandwidth and power consumption. A receiver 20 which receives data in packets on a number of the physical links at a clock frequency, reformats the packets into groups 21 and transmits the reformatted data on an output bus 22 at one of a plurality of data rates, is also disclosed.

公开(公告)号：ITTO20130824A1

公开(公告)日：2015-04-12

申请号：ITTO20130824

申请日：2013-10-11

Applicant: ST MICROELECTRONICS GRENOBLE 2 ,  ST MICROELECTRONICS SRL

Inventor： MANGANO DANIELE ,  URZI IGNAZIO ANTONINO

IPC: H04L49/111

公开(公告)号：FR3097345B1

公开(公告)日：2021-06-25

申请号：FR1906337

申请日：2019-06-13

Applicant: STMICROELECTRONICS GRAND OUEST SAS ,  ST MICROELECTRONICS GRENOBLE 2

Inventor： PALLARDY LOIC ,  URZI IGNAZIO ANTONINO ,  DURET JEAN-FRANCIS

IPC: G06F13/16

Abstract: Le circuit intégré (CI) comprend une unité de traitement (13) configurée pour démarrer avec un jeu d’instructions de démarrage, puis pour déterminer la taille des instructions d’un programme applicatif (APP) et éventuellement redémarrer sur sa propre initiative, en étant reconfigurée, afin qu’elle exécute les instructions du programme applicatif. Une seule mémoire de démarrage est par conséquent nécessaire. Figure pour l’abrégé : Fig 1

公开(公告)号：ITTO20111180A1

公开(公告)日：2013-06-22

申请号：ITTO20111180

申请日：2011-12-21

Applicant: ST MICROELECTRONICS GRENOBLE 2 ,  ST MICROELECTRONICS SRL

Inventor： MANGANO DANIELE ,  STRANO GIOVANNI ,  URZI IGNAZIO ANTONINO

IPC: H04L47/52

公开(公告)号：GB2494625A

公开(公告)日：2013-03-20

申请号：GB201115384

申请日：2011-09-06

Applicant: ST MICROELECTRONICS GRENOBLE 2

Inventor： URZI IGNAZIO ANTONINO ,  GRACIANNETTE NICOLAS

IPC: G06F13/16 ,  G06F21/60 ,  G06F21/62

Abstract: A data processing system has a security engine, such as a data scrambler, which processes data transferred to and from a memory. Memory operations are passed to the engine and the memory controller in parallel. The time the operation is passed to the memory controller may be controlled, such that the delay in the engine is less than or equal to the delay in the memory controller. The system may adjust the time based on delay information from the memory controller and the engine. This information may be the latency. The information may be determined from the time between a memory operation being received and the engine being ready to process the data.

公开(公告)号：ITTO20120851A1

公开(公告)日：2014-03-29

申请号：ITTO20120851

申请日：2012-09-28

Applicant: ST MICROELECTRONICS GRENOBLE 2 ,  ST MICROELECTRONICS SRL

Inventor： MANGANO DANIELE ,  URZI IGNAZIO ANTONINO

公开(公告)号：GB2497314A

公开(公告)日：2013-06-12

申请号：GB201120959

申请日：2011-12-06

Applicant: ST MICROELECTRONICS GRENOBLE 2 ,  ST MICROELECTRONICS RES & DEV ,  ST MICROELECTRONICS SA

Inventor： FERRIS ANDREW ,  URZI IGNAZIO ANTONINO ,  TEISSIER PASCAL

IPC: G06F13/40

Abstract: An integrated circuit has two blocks, which may be transmitters or may be receivers. The first transmits n bits and the second transmits m bits. The blocks can be configured to operate on two independent busses or can be configured to operate on a single n+m bit bus. The blocks may have the same circuitry, connected by a communication channel. The blocks may be arranged symmetrically about the channel. When operating on a single bus, one block may be a master and the other a slave. In this mode, a clock signal may be supplied by only one of the two blocks. One of the blocks may be put into a low power mode while the second block operates independently. The circuit may be used in video processing, the combined bus being used for three dimensional images and the separate busses being used for two dimensional images.