公开(公告)号：DE69132190T2

公开(公告)日：2000-10-05

申请号：DE69132190

申请日：1991-11-26

Applicant: ST MICROELECTRONICS INC

Inventor： LIOU FU-TAI ,  CHEN FUSEN E

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52

Abstract: A method is provided for forming improved quality interlevel aluminum contacts in semiconductor integrated circuits. A contact opening is formed through an insulating layer. A barrier layer is deposited over the surface of the integrated circuit. An aluminum layer is then deposited at relatively low deposition rates at a temperature which allows improved surface migration of the deposited aluminum atoms. Aluminum deposited under these conditions tends to fill contact vias without the formation of voids. The low temperature deposition step can be initiated by depositing aluminum while a wafer containing the integrated circuit device is being heated from cooler temperatures within the deposition chamber.

公开(公告)号：DE69228786T2

公开(公告)日：1999-11-11

申请号：DE69228786

申请日：1992-09-11

Applicant: ST MICROELECTRONICS INC

Inventor： CHEN FUSEN E ,  DIXIT GIRISH ANANT ,  MILLER ROBERT O

IPC: H01L21/265 ,  H01L21/02 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L27/00 ,  H01L27/10 ,  H01L27/11 ,  H01L21/329 ,  H01L27/07 ,  H01L21/82

Abstract: A method is provided for forming a polycrystalline silicon resistive load element of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A lightly doped conductive layer (24) having a conductivity of a first type. A oxide layer (26) is formed over the integrated circuit with a first opening (25) therethrough exposing a portion of the conductive layer (24). Using the oxide layer (26) as a mask, the exposed portion (25) of the conductive layer (24) is then implanted with a dopant of a second conductivity type to form a junction (27) between the exposed portion and the portion covered by the mask. A oxide region (30) is then formed on a portion of the oxide layer (26) in the first opening (25), over the junction (27) and over a portion of the exposed conductive layer (24) adjacent to the junction (27). A silicide (36) is formed over the exposed portion of the conductive layer (24).

公开(公告)号：DE69228786D1

公开(公告)日：1999-05-06

申请号：DE69228786

申请日：1992-09-11

Applicant: ST MICROELECTRONICS INC

Inventor： CHEN FUSEN E ,  DIXIT GIRISH ANANT ,  MILLER ROBERT O

IPC: H01L21/265 ,  H01L21/02 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L27/00 ,  H01L27/10 ,  H01L27/11 ,  H01L21/329 ,  H01L27/07 ,  H01L21/82

Abstract: A method is provided for forming a polycrystalline silicon resistive load element of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A lightly doped conductive layer (24) having a conductivity of a first type. A oxide layer (26) is formed over the integrated circuit with a first opening (25) therethrough exposing a portion of the conductive layer (24). Using the oxide layer (26) as a mask, the exposed portion (25) of the conductive layer (24) is then implanted with a dopant of a second conductivity type to form a junction (27) between the exposed portion and the portion covered by the mask. A oxide region (30) is then formed on a portion of the oxide layer (26) in the first opening (25), over the junction (27) and over a portion of the exposed conductive layer (24) adjacent to the junction (27). A silicide (36) is formed over the exposed portion of the conductive layer (24).

公开(公告)号：DE69232041D1

公开(公告)日：2001-10-11

申请号：DE69232041

申请日：1992-10-26

Applicant: ST MICROELECTRONICS INC

Inventor： DIXIT GIRISH ANANT ,  CHEN FUSEN E ,  MILLER ROBERT O

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/763 ,  H01L27/08

Abstract: A method for forming field oxide regions includes the formation of cavities in a semiconductor substrate. A layer of thermal oxide is then grown on the substrate. A layer of planarizing material is deposited over the device, filling the cavities. The planarizing layer is etched back to expose a portion of the cavities. A conformal layer of undoped oxide or a layer of polycrystalline silicon that is converted to oxide is deposited over the device, followed by a second layer of planarizing material, The planarizing material and conformal layer are then etched back to expose the active areas in the substrate.

公开(公告)号：DE69132190D1

公开(公告)日：2000-06-15

申请号：DE69132190

申请日：1991-11-26

Applicant: ST MICROELECTRONICS INC

Inventor： LIOU FU-TAI ,  CHEN FUSEN E

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52

Abstract: A method is provided for forming improved quality interlevel aluminum contacts in semiconductor integrated circuits. A contact opening is formed through an insulating layer. A barrier layer is deposited over the surface of the integrated circuit. An aluminum layer is then deposited at relatively low deposition rates at a temperature which allows improved surface migration of the deposited aluminum atoms. Aluminum deposited under these conditions tends to fill contact vias without the formation of voids. The low temperature deposition step can be initiated by depositing aluminum while a wafer containing the integrated circuit device is being heated from cooler temperatures within the deposition chamber.

公开(公告)号：DE69323513D1

公开(公告)日：1999-03-25

申请号：DE69323513

申请日：1993-07-08

Applicant: ST MICROELECTRONICS INC

Inventor： CHEN FUSEN E ,  DIXIT GIRISH ANANT ,  MILLER ROBERT O

IPC: H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L21/285

Abstract: A method is provided for patterning a submicron semiconductor layer of an integrated circuit, and an integrated circuit formed according to the same. A first conductive structure is formed over the integrated circuit. A dielectric is formed over the first conductive structure having a contact opening exposing a portion of the underlying first conductive layer. A barrier layer is formed in the bottom of the contact opening. A second, substantially conformal conductive layer is formed by chemical vapor deposition over the dielectric layer; along the sidewalls and in the bottom of the contact opening. A third conductive layer is then formed over the second conductive layer wherein the third conductive layer does not fill the contact opening. The second and third conductive layers are etched to form an interconnect substantially over the contact opening.

公开(公告)号：DE69327600T2

公开(公告)日：2000-06-21

申请号：DE69327600

申请日：1993-02-24

Applicant: ST MICROELECTRONICS INC

Inventor： CHEN FUSEN E ,  MILLER ROBERT O ,  DIXIT GIRISH ANANT

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/768

公开(公告)号：DE69323513T2

公开(公告)日：1999-08-12

申请号：DE69323513

申请日：1993-07-08

Applicant: ST MICROELECTRONICS INC

Inventor： CHEN FUSEN E ,  DIXIT GIRISH ANANT ,  MILLER ROBERT O

IPC: H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L21/285

Abstract: A method is provided for patterning a submicron semiconductor layer of an integrated circuit, and an integrated circuit formed according to the same. A first conductive structure is formed over the integrated circuit. A dielectric is formed over the first conductive structure having a contact opening exposing a portion of the underlying first conductive layer. A barrier layer is formed in the bottom of the contact opening. A second, substantially conformal conductive layer is formed by chemical vapor deposition over the dielectric layer; along the sidewalls and in the bottom of the contact opening. A third conductive layer is then formed over the second conductive layer wherein the third conductive layer does not fill the contact opening. The second and third conductive layers are etched to form an interconnect substantially over the contact opening.

公开(公告)号：DE69133549D1

公开(公告)日：2006-11-16

申请号：DE69133549

申请日：1991-11-01

Applicant: ST MICROELECTRONICS INC

Inventor： CHEN FUSEN E ,  LIOU FU-TAI ,  LIN YIH-SHUNG ,  DIXIT GIRISH A ,  WEI CHE-CHIA

IPC: H01L21/28 ,  H01L21/285 ,  C23C16/02 ,  C23C16/20 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/485 ,  H01L23/532

Abstract: A method is provided for depositing aluminum thin film layers to form improved quality contacts in a semiconductor integrated circuit device. All or some of the deposition process occurs at relatively low deposition rates at a temperature which allows improved surface migration of the deposited aluminum atoms. Aluminum deposited under these conditions tends to fill contact vias without the formation of voids. The low temperature deposition step can be initiated by depositing aluminum while a wafer containing the integrated circuit device is being heated from cooler temperatures within the deposition chamber.

公开(公告)号：DE69232041T2

公开(公告)日：2002-04-18

申请号：DE69232041

申请日：1992-10-26

Applicant: ST MICROELECTRONICS INC

Inventor： DIXIT GIRISH ANANT ,  CHEN FUSEN E ,  MILLER ROBERT O

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/763 ,  H01L27/08

Abstract: A method for forming field oxide regions includes the formation of cavities in a semiconductor substrate. A layer of thermal oxide is then grown on the substrate. A layer of planarizing material is deposited over the device, filling the cavities. The planarizing layer is etched back to expose a portion of the cavities. A conformal layer of undoped oxide or a layer of polycrystalline silicon that is converted to oxide is deposited over the device, followed by a second layer of planarizing material, The planarizing material and conformal layer are then etched back to expose the active areas in the substrate.