公开(公告)号：FR2820903A1

公开(公告)日：2002-08-16

申请号：FR0101885

申请日：2001-02-12

Applicant: ST MICROELECTRONICS SA

Inventor： AITOUARAB LEILA

IPC: H03K3/356 ,  H03K17/10 ,  H03K17/693 ,  H03K17/08 ,  G11C16/08

Abstract: A voltage-switching device includes a high-voltage translator connected to a high-voltage node receiving either a low-voltage logic level or a high-voltage level as a function of a low-voltage/high-voltage mode control signal to provide at least one output signal as a function of this mode control signal and of a switching control signal. A voltage-level switching circuit is controlled by output signals from the high-voltage translator and by the mode control signal and the switching control signal for application, as output voltage levels, of either ground or the low-voltage logic level in low-voltage mode or the high-voltage level in high-voltage mode.

公开(公告)号：FR2814583A1

公开(公告)日：2002-03-29

申请号：FR0012070

申请日：2000-09-22

Applicant: ST MICROELECTRONICS SA

Inventor： AITOUARAB LEILA

IPC: G11C7/06 ,  G11C16/26 ,  G11C17/00

Abstract: The method for reading a memory cell by a read circuit comprises the following steps: The provision of a reference voltage (Vref) representative of a reference current (Iref) as the image of current (If) traversing the memory cell when the control voltage (VC) is equal to the reference voltage. The provision of a read voltage representative of a read current as the image of current (IVDD) traversing the memory cell when the control voltage is equal to the supply voltage. The comparison of the read voltage to the reference voltage and the provision of binary information (ETAT) regarding the state of the memory cell. The second step comprises the following substeps: The application of the reference control voltage (VCref), and the charging of a reference capacitor with the reference current in the course of a first time interval. The provision of a cell voltage (Vcel) on the reference capacitor poles, so that the reference voltage is equal to the capacitor voltage at the end of the first time interval. The capacitor voltage (Vf) increases with a first slope in proportion to the reference current during the first time interval, and then remains constant. The third step comprises the following substeps: The application of the reference control voltage, and the charging of a measuring capacitor with the reference current in the course of the first time interval. The application of the read control voltage, and the discharging of the measuring capacitor. The provision of the measuring voltage on the capacitor poles at the end of a second time interval. The measuring capacitor voltage increases during the first time interval with a second slope, which is greater than the first slope, in proportion to the reference current, and then decreases with a third slope in proportion to the read current, where the third slope depends on the programmed/erased state of cell. The reference control voltage is between null and a first threshold value, and the read control voltage is between the first and second threshold values. The reference capacitance is lower than the measuring capacitance. The reference current is equal to the cell current obtained when the reference control voltage is applied, or to a shift current provided by an external source, or to the sum of the shift current and the cell current. The reset is by discharging both capacitors. The read circuit comprises the reference voltage measuring circuit, the read voltage measuring circuit and a comparator comparing the read voltage to the reference voltage and providing the binary information on the cell state. A read-only memory comprises the read circuit for implementing the method.

公开(公告)号：FR2823362B1

公开(公告)日：2005-03-11

申请号：FR0104750

申请日：2001-04-06

Applicant: ST MICROELECTRONICS SA

Inventor： AITOUARAB LEILA ,  THOMAS SIGRID

IPC: G11C7/06 ,  G11C16/26

Abstract: In a device for reading memory cells, a precharging circuit is connected to a memory cell to be read and to a reference cell associated with the memory cell to be read. The precharging circuit precharges the output of the differential amplifier to a predetermined voltage level. The reading device further includes an inverter having a high threshold and a low threshold connected to the output of the differential amplifier. The predetermined voltage level corresponds to an intermediate level between the high and low thresholds.

公开(公告)号：FR2820903B1

公开(公告)日：2003-06-06

申请号：FR0101885

申请日：2001-02-12

Applicant: ST MICROELECTRONICS SA

Inventor： AITOUARAB LEILA

IPC: H03K3/356 ,  H03K17/10 ,  H03K17/693 ,  H03K17/08 ,  G11C16/08

Abstract: A voltage-switching device includes a high-voltage translator connected to a high-voltage node receiving either a low-voltage logic level or a high-voltage level as a function of a low-voltage/high-voltage mode control signal to provide at least one output signal as a function of this mode control signal and of a switching control signal. A voltage-level switching circuit is controlled by output signals from the high-voltage translator and by the mode control signal and the switching control signal for application, as output voltage levels, of either ground or the low-voltage logic level in low-voltage mode or the high-voltage level in high-voltage mode.

公开(公告)号：FR2823362A1

公开(公告)日：2002-10-11

申请号：FR0104750

申请日：2001-04-06

Applicant: ST MICROELECTRONICS SA

Inventor： AITOUARAB LEILA ,  THOMAS SIGRID

IPC: G11C7/06 ,  G11C16/26

Abstract: The device comprises a differential amplifier with inputs (e1,e2) connected to the bit lines of a memory cell (Cmem) and a reference cell (Cref), respectively, a circuit for precharging the output of the differential amplifier to a predetermined voltage level (V1) which is intermediate between the high logic level and the low logic level, and a Schmitt trigger circuit, which is an inverter with a threshold, delivering the output signal DATAOUT. The intermediate voltage level corresponds to the means of high and low logic levels, which is (Vdd/2). The output precharge circuit comprises an upper branch with two p-MOS transistors and a lower branch with two n-MOS transistors; each branch comprises a transistor connected as a diode and a transistor controlled by a precharge signal. The device also comprises an equilibration circuit for equilibrating the two inputs (e1,e2) of the differential amplifier, which is activated in the precharge phase. The output precharge circuit is deactivated after the equilibration circuit. An integrated circuit comprises the device for reading memory cells, which are of SRAM type.