公开(公告)号：FR2831289B1

公开(公告)日：2004-01-23

申请号：FR0113478

申请日：2001-10-19

Applicant: ST MICROELECTRONICS SA

Inventor： ROCHE FRANCK ,  BASSET PHILIPPE

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/34 ,  G06F9/355 ,  G06F12/02 ,  G06F9/44 ,  G06F15/00

Abstract: A microprocessor includes a processing unit, an address bus connected to an addressable memory space, and executes instructions from an instruction set for accessing the addressable memory space. The addressable memory space is for a lower memory area and an extended memory area. The instruction set includes a first instruction group for accessing the lower memory area, and a second instruction group that is distinct from the first instruction group for accessing the extended memory area.

公开(公告)号：FR2831289A1

公开(公告)日：2003-04-25

申请号：FR0113478

申请日：2001-10-19

Applicant: ST MICROELECTRONICS SA

Inventor： ROCHE FRANCK ,  BASSET PHILIPPE

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/34 ,  G06F9/355 ,  G06F12/02 ,  G06F9/44 ,  G06F15/00

Abstract: The microprocessor comprises a processing unit (1) and an addressable memory space (2). This comprises a base memory zone (2a) and an extended memory zone (2b). Two instruction sets are provided for accessing the two respective memory zones, such that when one set is in use, access may only be gained to the respective memory zone. The microprocessor comprises a processing unit (1) and a connection system with access to an addressable memory space (2). The processor is able to execute the instructions derived from a set comprising instructions for accessing the memory space. The memory space has a base memory zone (2a) and an extended memory zone (2b). The instruction set includes a first set of instructions for accessing the base memory zone and a second set of instructions for accessing the extended memory zone. The microprocessor includes a system for preventing any access to the extended memory zone when the processor is executing instructions from the first instruction set. The microprocessor is thus forced to use the appropriate memory region when executing instructions from one or other of the two memory areas.

公开(公告)号：DE60204036D1

公开(公告)日：2005-06-09

申请号：DE60204036

申请日：2002-10-11

Applicant: ST MICROELECTRONICS SA

Inventor： ROCHE FRANCK ,  BASSET PHILIPPE

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/34 ,  G06F9/355 ,  G06F12/02

Abstract: A microprocessor includes a processing unit, an address bus connected to an addressable memory space, and executes instructions from an instruction set for accessing the addressable memory space. The addressable memory space is for a lower memory area and an extended memory area. The instruction set includes a first instruction group for accessing the lower memory area, and a second instruction group that is distinct from the first instruction group for accessing the extended memory area.