公开(公告)号：JP2002198945A

公开(公告)日：2002-07-12

申请号：JP2001363669

申请日：2001-11-29

Applicant: ST MICROELECTRONICS SA

Inventor： ROCHE FRANCK ,  TARAYRE PIERRE

IPC: H04L7/04 ,  G06F13/42

Abstract: PROBLEM TO BE SOLVED: To provide a method for transmitting data between two devices (D1, D2) which can restrain a clock line to an electric potential representing a logic value B opposite to a logic value A respectively using a clock line (CK) maintained at the default value of the logic value A and at least one data line (DT). SOLUTION: By the method of this invention, both devices restrain the clock line to B when the data is transmitted, the device to which the data is transmitted doesn't release the clock line when the device doesn't end reading out the data, and the device which transmits the data maintains the data on the data line at least until when the clock line is released by the device to which the data is transmitted. This method is especially applied to the communication between a microcomputer and a microprocessor.

公开(公告)号：DE602004007835T2

公开(公告)日：2008-04-10

申请号：DE602004007835

申请日：2004-01-14

Applicant: ST MICROELECTRONICS SA

Inventor： PADMANABHA GOSAGAN ,  DAVIDESCU DRAGOS ,  ROCHE FRANCK

IPC: G06F9/38 ,  G06F9/06 ,  G06F9/30 ,  G06F9/42 ,  G06F9/46 ,  G06F11/30 ,  G06F12/16

Abstract: The microprocessor has a CPU with registers containing a contextual data and a pointer of stack (SP, SPH, SPL). A memory (MEM2) has a stack (STK) for backup of the contextual data. The CPU is arranged to backup the contextual data contained in a variable number of registers according to a flag value stored in a register (CCR, CR) to backup, at a time of shifting from one program to another. An independent claim is also included for a process of management of stack of microprocessor.

公开(公告)号：FR2817432B1

公开(公告)日：2003-01-24

申请号：FR0015387

申请日：2000-11-29

Applicant: ST MICROELECTRONICS SA

Inventor： ROCHE FRANCK ,  TARAYRE PIERRE

IPC: H04L7/04 ,  G06F13/42 ,  H04L29/08 ,  G06F15/163

Abstract: Two devices (D1,D2) may transmit data using clock thread (CK) and at least a data thread (DT). The clock thread is maintained by default to a logical value A that may be converted to an electric potential representing a logical value B inverse of A. The two devices may convert B to the CK at the time of data transmission. A target device to which the data is sent does not loose the CK since it does not read the data. The data-sending device maintains it until the CK is released by the device to which data is targeted. Independent claims are included for: (a) a data transmission-reception device (b) a synchronous data transmission device (c) an interface circuit for data transmission in master-slave configuration

公开(公告)号：DE60000112T2

公开(公告)日：2002-11-14

申请号：DE60000112

申请日：2000-01-06

Applicant: ST MICROELECTRONICS SA

Inventor： ROCHE FRANCK

IPC: G06F12/14

Abstract: The secure access system accesses a microprocessor with an address and digital word bus and a register (3) and address decoder (2). A number of protection circuits (1) are associated with the register providing access. After initialization (RESET) of the microprocessor access is blocked, only allowing access after sending a set of N digital pass words during the first operation set.

公开(公告)号：FR2817417A1

公开(公告)日：2002-05-31

申请号：FR0015307

申请日：2000-11-28

Applicant: ST MICROELECTRONICS SA

Inventor： ROCHE FRANCK ,  NARCHE PASCAL ,  RUAT LUDOVIC

IPC: G01R31/317 ,  G06F11/22 ,  H03K21/38 ,  G06F11/30 ,  G06F13/00 ,  H03K19/003

Abstract: The microprocessor has a counter (CNTR) with a count input (E1) and a reset input (E2). The reset input is controlled by a signal (CS) present on a microprocessor pin (P2). The control signal is set either internally (R1) or externally to a logic value that ensures the counter reset is active during the initialization of the microprocessor.

公开(公告)号：DE60204036D1

公开(公告)日：2005-06-09

申请号：DE60204036

申请日：2002-10-11

Applicant: ST MICROELECTRONICS SA

Inventor： ROCHE FRANCK ,  BASSET PHILIPPE

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/34 ,  G06F9/355 ,  G06F12/02

Abstract: A microprocessor includes a processing unit, an address bus connected to an addressable memory space, and executes instructions from an instruction set for accessing the addressable memory space. The addressable memory space is for a lower memory area and an extended memory area. The instruction set includes a first instruction group for accessing the lower memory area, and a second instruction group that is distinct from the first instruction group for accessing the extended memory area.

公开(公告)号：FR2820523A1

公开(公告)日：2002-08-09

申请号：FR0101681

申请日：2001-02-08

Applicant: ST MICROELECTRONICS SA

Inventor： ROCHE FRANCK ,  LAFARGUE NICOLAS

IPC: G06F5/01 ,  G06F7/575 ,  G06F7/76 ,  G06F9/30 ,  G06F9/302 ,  G06F9/315

Abstract: A microprocessor comprises a central processing unit having an arithmetic and logic unit with two inputs and one input fed-back to one of the inputs through a data path. The arithmetic and logic unit performs arithmetic and logic operations on binary words temporarily stored within registers in the central processing unit. The central processing unit further includes a shift unit in the data path of the arithmetic and logic unit for performing operations to shift bits in the binary words applied thereto. A selection circuit selects a shift operation to be performed. An inverting circuit inverts the ordering of the bits in the binary words applied thereto, which are in the data path of the arithmetic and logic unit, and a selection circuit selects the inversion operation when the latter is required.

公开(公告)号：FR2820223A1

公开(公告)日：2002-08-02

申请号：FR0101277

申请日：2001-01-31

Applicant: ST MICROELECTRONICS SA

Inventor： ROCHE FRANCK

IPC: G06F12/06 ,  G06F12/02

Abstract: Microprocessor comprises a CPU (2), a data bus (4) and an address bus (8) for access to program memory space with a size greater that that addressable with the address bus. Accordingly the memory space is divided into pages, which are addressed by the processor using a page register (PR) in which page numbers are memorized. The microprocessor comprises means for concatenating page register contents with those on the address bus when these correspond to an address in program memory. The invention also relates to a corresponding method for accessing program memory that is divided into pages.

公开(公告)号：FR2817362A1

公开(公告)日：2002-05-31

申请号：FR0015390

申请日：2000-11-29

Applicant: ST MICROELECTRONICS SA

Inventor： ROCHE FRANCK ,  BOUQUIER THIERRY

IPC: G06F11/267 ,  G06F11/30 ,  G06F9/06 ,  G06F12/00 ,  G06F11/36

Abstract: Microprocessor (MP2) includes a device (CPU) to protect contextual data (CCo,Ao,Xo,PCho,PCIo) in its stack (STK) at the time of a interruption of a test program. A delivery device brings a data (CCo,Ao) present in the stack (STK) to an I/O port of the microprocessor at the beginning of a test session starting at the top of the stack. A pointer of the stack (SP) is decremented by a value corresponding to the number of delivered contextual data. An Independent claim is included for: (a) a method of managing a memory space of the microprocessor after the interruption by a test program for registering context data in a stack

公开(公告)号：FR2850176B1

公开(公告)日：2005-04-15

申请号：FR0300442

申请日：2003-01-16

Applicant: ST MICROELECTRONICS SA

Inventor： LENDRE SANDRINE ,  PLOURDE OLIVIER ,  ROCHE FRANCK

IPC: G06F1/04 ,  G06F1/12

Abstract: The circuit has a decounter (DCNT) producing a time base signal (TBS) from a clock signal (H1) and count value (TBVAL1). A counter, register, and logic circuit (CNT,CREG,CCT) find another count value (TBVAL2) equal to a number of periods of another clock signal (H2) appearing during a time interval equal to periods of the signal (TBS). The decounter produces another time base signal from the signal (H2) and value (TBVAL2).