公开(公告)号：FR2786569B1

公开(公告)日：2001-02-09

申请号：FR9815149

申请日：1998-11-27

Applicant: ST MICROELECTRONICS SA

Inventor： BOIVIN PHILIPPE

IPC: G11C29/04 ,  G11C29/24 ,  G11C29/50 ,  G01R31/3187 ,  G11C29/00

Abstract: A testing circuit made on a silicon wafer including a plurality of identical cells, each of which includes a primary capacitor of given characteristics, which includes a test capacitor of same characteristics as each primary capacitor and of surface at least equal to the sum of the surfaces of the primary capacitors.

公开(公告)号：DE69700132D1

公开(公告)日：1999-04-15

申请号：DE69700132

申请日：1997-10-30

Applicant: ST MICROELECTRONICS SA

Inventor： FOURNEL RICHARD ,  BOIVIN PHILIPPE

IPC: H01L21/8246 ,  H01L27/112

公开(公告)号：FR2826779A1

公开(公告)日：2003-01-03

申请号：FR0108776

申请日：2001-07-02

Applicant: ST MICROELECTRONICS SA

Inventor： BOIVIN PHILIPPE ,  LA ROSA FRANCESCO

IPC: H01L21/28 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8247 ,  H01L27/02 ,  H01L27/04 ,  H01L27/088 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L23/60

Abstract: The circuit has an antistatic contact (21) formed of a thin oxide layer (22), present between a polysilicon line (4) and a silicon substrate (1). The thickness of the oxide layer is in the range of 0.002 - 0.015 mu m, such that a current flows through the oxide layer due to tunnel effect, when the voltage across the polysilicon line is less than or greater than specific threshold values. An Independent claim is included for integrated circuit manufacturing method.

公开(公告)号：FR2799050A1

公开(公告)日：2001-03-30

申请号：FR9912253

申请日：1999-09-24

Applicant: ST MICROELECTRONICS SA

Inventor： BOIVIN PHILIPPE

IPC: H01L21/28 ,  H01L29/788 ,  H01L21/8247 ,  G11C17/00

Abstract: The first conductive layer has an appreciable thickness (h) in front of its width (W) and it is etched with a view to rounding-off its corners. An Independent claim is included for a corresponding structure.

公开(公告)号：FR2786569A1

公开(公告)日：2000-06-02

申请号：FR9815149

申请日：1998-11-27

Applicant: ST MICROELECTRONICS SA

Inventor： BOIVIN PHILIPPE

IPC: G11C29/04 ,  G11C29/24 ,  G11C29/50 ,  G01R31/3187 ,  G11C29/00

Abstract: Test circuit comprises a silicon wafer with a plurality of identical cells (10) each having an elementary capacity (C2) with given characteristics. In addition there is a test capacity (C2') with thee same characteristics as each elementary capacity and with a surface area at least equal to the sum of the surfaces of the elementary capacities.

公开(公告)号：DE69700132T2

公开(公告)日：1999-07-01

申请号：DE69700132

申请日：1997-10-30

Applicant: ST MICROELECTRONICS SA

Inventor： FOURNEL RICHARD ,  BOIVIN PHILIPPE

IPC: H01L21/8246 ,  H01L27/112