公开(公告)号：DE69631619T2

公开(公告)日：2004-12-23

申请号：DE69631619

申请日：1996-06-18

Applicant: ST MICROELECTRONICS SA

Inventor： DIAZ NAVA MARIO ,  BULONE JOSEPH

IPC: H03M13/15 ,  H03M13/35 ,  H04L7/04 ,  H03M13/11

Abstract: The packets contain n data of p bits. The first interconnection matrix (M ) corresponds to a pth. power polynomial. Each data received defines a new packet and the sum includes the data of the preceding packet, modified by a second interconnection matrix (M ) corresponding to an nth. power of the first matrix. The data comprise words (B) of which p bits form vector components processed by the matrices. For each jth. bit of the received word, the summer (14) receiving the jth. bit has an output associated with the (j-1)th. bit, modified by the first matrix, and the jth. bit of the word preceding the new packet, modified by the second matrix of the npth. power polynomial.

公开(公告)号：DE602004018646D1

公开(公告)日：2009-02-05

申请号：DE602004018646

申请日：2004-01-19

Applicant: ST MICROELECTRONICS SA

Inventor： HARRAND MICHEL ,  BULONE JOSEPH

IPC: G11C11/406 ,  G11C29/00

Abstract: The method involves successively performing measurements on a selected group of memory cells (CL) at a lower measurement frequency than a refresh frequency of unselected cells such that each selected group of cells is refreshed more slowly than unselected cells of the memory. The retention times of each group of cells are successively measured, and the unselected cells are refreshed successively. An independent claim is also included for a dynamic random access memory device.

公开(公告)号：FR2820874B1

公开(公告)日：2003-05-30

申请号：FR0101934

申请日：2001-02-13

Applicant: ST MICROELECTRONICS SA

Inventor： HARRAND MICHEL ,  BULONE JOSEPH

IPC: G11C7/10 ,  G11C8/12 ,  G11C11/406 ,  G11C11/4076 ,  G11C8/00 ,  G06F12/08 ,  G11C11/40

Abstract: A method to manage fast random access of a DRAM memory is described. The method includes steps of: dividing the memory into memory banks accessible independently in read and write mode; identifying the address of the bank concerned by a current request and comparing the address of the bank concerned by a current request with the addresses of the N-1 banks previously requested. N is an integral number of cycles necessary for executing a request. If the address of the bank concerned by a current request is equal to the address of a bank corresponding to one of the N-1 previous requests, then the method further includes steps of suspending and memorizing the current request until the previous request involving the same bank is executed, otherwise the current request is executed.

公开(公告)号：DE69631619D1

公开(公告)日：2004-04-01

申请号：DE69631619

申请日：1996-06-18

Applicant: ST MICROELECTRONICS SA

Inventor： DIAZ NAVA MARIO ,  BULONE JOSEPH

IPC: H03M13/15 ,  H03M13/35 ,  H04L7/04 ,  H03M13/11

Abstract: The packets contain n data of p bits. The first interconnection matrix (M ) corresponds to a pth. power polynomial. Each data received defines a new packet and the sum includes the data of the preceding packet, modified by a second interconnection matrix (M ) corresponding to an nth. power of the first matrix. The data comprise words (B) of which p bits form vector components processed by the matrices. For each jth. bit of the received word, the summer (14) receiving the jth. bit has an output associated with the (j-1)th. bit, modified by the first matrix, and the jth. bit of the word preceding the new packet, modified by the second matrix of the npth. power polynomial.

公开(公告)号：FR2820874A1

公开(公告)日：2002-08-16

申请号：FR0101934

申请日：2001-02-13

Applicant: ST MICROELECTRONICS SA

Inventor： HARRAND MICHEL ,  BULONE JOSEPH

IPC: G11C7/10 ,  G11C8/12 ,  G11C11/406 ,  G11C11/4076 ,  G11C8/00 ,  G06F12/08 ,  G11C11/40

Abstract: A method to manage fast random access of a DRAM memory is described. The method includes steps of: dividing the memory into memory banks accessible independently in read and write mode; identifying the address of the bank concerned by a current request and comparing the address of the bank concerned by a current request with the addresses of the N-1 banks previously requested. N is an integral number of cycles necessary for executing a request. If the address of the bank concerned by a current request is equal to the address of a bank corresponding to one of the N-1 previous requests, then the method further includes steps of suspending and memorizing the current request until the previous request involving the same bank is executed, otherwise the current request is executed.