公开(公告)号：FR2821456A1

公开(公告)日：2002-08-30

申请号：FR0102701

申请日：2001-02-28

Applicant: ST MICROELECTRONICS SA

Inventor： ROCHE FRANCK ,  CAVALLI DIDIER

IPC: G06F12/06 ,  G06F13/16 ,  G06F13/36 ,  G06F13/40 ,  G06F15/76 ,  G06F13/368

Abstract: The invention relates to a microprocessor which is connected to a first memory space (4) by means of a first bus (AP, DIP, DOP, RWP) and to a second memory space (5) by means of a second bus (AD, DID, DODD, RWD). The inventive microprocessor comprises a processing unit (2), which is fitted with a program bus (PC, INS) and a data bus (A, DBO, DBI, RW), and an interface unit (3) which is connected, on one side, to the program bus (PC, INS) and the data bus (A, DBO, DBI, RW) and, on the other side, to the first bus (AP, DIP, DOP, RWP) and the second bus (AD, DID, DOP, RWD). The interface unit (3) comprises switching means (23, 25, 26) for connecting the program bus and the data bus respectively either to the first bus or the second bus according to the requests sent by the processing unit for access to the program (NPR) and to the data (NDR) respectively.

公开(公告)号：FR2821456B1

公开(公告)日：2003-06-20

申请号：FR0102701

申请日：2001-02-28

Applicant: ST MICROELECTRONICS SA

Inventor： ROCHE FRANCK ,  CAVALLI DIDIER

IPC: G06F12/06 ,  G06F13/16 ,  G06F13/36 ,  G06F13/40 ,  G06F15/76 ,  G06F13/368

Abstract: A microprocessor is connected to a first memory space through a first bus and to a second memory space through a second bus. The microprocessor includes a processing unit that includes a program bus and a data bus, and an interface unit connected, on one side, to the program bus and to the data bus and, on the other side, to the first and second buses. The interface includes a switching circuit for connecting the program bus and the data bus, respectively, to either the first bus or the second bus, in accordance with respective requests for accessing the program and data sent by the processing unit.