公开(公告)号：JP2004158860A

公开(公告)日：2004-06-03

申请号：JP2003375156

申请日：2003-11-05

Applicant: St Microelectronics Sa ,  エスティマイクロエレクトロニクス エスエー

Inventor： MAZOYER PASCALE ,  VILLARET ALEXANDRE ,  SKOTNICKI THOMAS

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: B82Y10/00 ,  G11C2216/08 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/7888

Abstract: PROBLEM TO BE SOLVED: To realize a single transistor memory cell having the characteristics of a conventional SRAM and a flash memory. SOLUTION: In the memory circuit including at least one memory cell made of a single transistor, an insulating layer is formed between the gate and the channel regions of the transistor so that the insulating layer is parallel with each of the surfaces of the regions; a continuum of potential wells which are arranged with certain distances separated from the gate and the channel region, is formed in the insulating layer. Since the potential wells can include charges, two memory states concerning the memory cell state, i.e. "0"state, and "1" state can be defined by moving the charges to a first entrapping region direction next to the source region, or a second entrapping region direction next to the drain region. COPYRIGHT: (C)2004,JPO

公开(公告)号：WO03017362A8

公开(公告)日：2003-04-03

申请号：PCT/FR0202887

申请日：2002-08-14

Applicant: ST MICROELECTRONICS SA ,  MAZOYER PASCALE ,  CAILLAT CHRISTIAN

Inventor： MAZOYER PASCALE ,  CAILLAT CHRISTIAN

IPC: H01L21/28 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L27/10888

Abstract: The invention concerns an integrated circuit comprising a substrate (1), at least a capacitor (9) arranged above the substrate (1) and provided with a first electrode (5), a second electrode (8), and a dielectric (7) arranged between the two electrodes, at least a connecting feedthrough between the substrate (1) and a conductive level located above the capacitor (9), and a dielectric material covering the substrate (1) and enclosing the capacitor (9) and the feedthrough. The feedthrough comprises a first portion (18) arranged between the substrate and the lower level of the first electrode, a second portion (6) arranged between the lower level of the first electrode and the upper level of the first electrode, and a third portion (12) in contact with the first electrode and flush with said conductive level, the second portion being made of the same material as the first electrode of the capacitor.

Abstract translation: 本发明涉及一种集成电路，该集成电路包括衬底（1），布置在衬底（1）上方并且设置有第一电极（5），第二电极（8）和电介质（7）的至少一个电容器（9） 布置在所述两个电极之间，所述衬底（1）和位于所述电容器（9）上方的导电层之间的至少一个连接馈通，以及覆盖所述衬底（1）并封闭所述电容器（9）和所述馈通的介电材料。 馈通包括布置在基板与第一电极的下层之间的第一部分（18），布置在第一电极的下层与第一电极的上层之间的第二部分（6），以及第三部分 （12）与所述第一电极接触并与所述导电层平齐，所述第二部分由与所述电容器的第一电极相同的材料制成。

公开(公告)号：FR2828764B1

公开(公告)日：2004-01-23

申请号：FR0110868

申请日：2001-08-16

Applicant: ST MICROELECTRONICS SA

Inventor： MALLARDEAU CATHERINE ,  MAZOYER PASCALE ,  PIAZZA MARC

IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/108

Abstract: This integrated circuit comprises a capacitor ( 23 ) formed above a substrate ( 1 ) inside a first cavity in a dielectric and comprising a first electrode, a second electrode, a thin dielectric layer placed between the two electrodes, and a structure ( 7 ) for connection to the capacitor. The connection structure is formed at the same level as the capacitor in a second cavity narrower than the first cavity, the said second cavity being completely filled by an extension of at least one of the electrodes of the capacitor.

公开(公告)号：FR2824423A1

公开(公告)日：2002-11-08

申请号：FR0105881

申请日：2001-05-02

Applicant: ST MICROELECTRONICS SA

Inventor： MAZOYER PASCALE ,  CAILLAT CHRISTIAN

IPC: H01L21/02 ,  H01L21/314 ,  H01L23/522 ,  H01L21/71 ,  H01L21/768

公开(公告)号：FR2857150A1

公开(公告)日：2005-01-07

申请号：FR0307960

申请日：2003-07-01

Applicant: ST MICROELECTRONICS SA

Inventor： JACQUET FRANCOIS ,  CANDELLIER PHILIPPE ,  CERUTTI ROBIN ,  CORONEL PHILIPPE ,  MAZOYER PASCALE

IPC: G11C11/405 ,  H01L27/06 ,  H01L27/108 ,  H01L27/12 ,  G11C11/401 ,  H01L21/8242

Abstract: The unit has a pair of cells (C1, C2) for storing two independent bits and including field effect transistors with grid (4, 14), respectively. A channel is arranged in a source zone (102), and the two transistors are arranged in between the source zone and a drain zone. An electrode of single polarization (24) is arranged between intermediate portions (1, 11) of the two transistors. An independent claim is also included for a method for manufacturing an integrated DRAM on a surface of a substrate.

公开(公告)号：FR2784798A1

公开(公告)日：2000-04-21

申请号：FR9813034

申请日：1998-10-14

Applicant: ST MICROELECTRONICS SA

Inventor： CIAVATTI JEROME ,  MAZOYER PASCALE

IPC: H01L21/8242

公开(公告)号：FR2969392B1

公开(公告)日：2013-02-08

申请号：FR1060638

申请日：2010-12-16

Applicant: ST MICROELECTRONICS SA ,  ST MICROELECTRONICS CROLLES 2

Inventor： MAZOYER PASCALE ,  HALIMAOUI AOMAR

IPC: H01M2/02 ,  H01M8/16

公开(公告)号：FR2930371A1

公开(公告)日：2009-10-23

申请号：FR0802106

申请日：2008-04-16

Applicant: ST MICROELECTRONICS SA

Inventor： MAZOYER PASCALE ,  BOSSU GERMAIN

IPC: H01L21/8239 ,  G11C11/34 ,  G11C16/02

Abstract: Une structure mémoire comportant un transistor d'accès (TR) connecté en série avec un élément résistif programmable (EM), caractérisé en ce que ledit élément résistif programmable comporte sur un substrat semi-conducteur (110) ; une couche isolante (170) disposant d'un évidement comportant :- une première couche (140) tapissant les surfaces latérales et le fond dudit évidemment et imperméable à la diffusion de métal ;- une seconde couche (150) composé d'un matériau poreux sur ladite première couche ; :- une troisième couche (160) de matériau métallique permettant de réaliser une électrode de contact susceptible de diffusion au sein dudit matériau poreux constitué de la seconde couche.La diffusion des ions métalliques au sein de ladite seconde couche étant commandée par l'action conjointe d'un champ électrique et de la température.Un procédé de fabrication est également décrit.

公开(公告)号：FR2856521A1

公开(公告)日：2004-12-24

申请号：FR0307559

申请日：2003-06-23

Applicant: ST MICROELECTRONICS SA

Inventor： MAZOYER PASCALE ,  RANICA ROSSELLA

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/786 ,  H01L29/78

Abstract: The transistor has a gate region (18), source region (12) and drain region (14) formed in an active zone. A channel (16) is provided between the source and drain regions such that the gate region extends above the channel. A trapping zone (22) traps electrons to create a potential reservoir under the channel to vary a threshold voltage of the transistor. An independent claim is also included for a method of fabricating a metal oxide semiconductor type transistor.

公开(公告)号：FR2852441A1

公开(公告)日：2004-09-17

申请号：FR0303194

申请日：2003-03-14

Applicant: ST MICROELECTRONICS SA

Inventor： CORONEL PHILIPPE ,  MAZOYER PASCALE ,  SKOTNICKI THOMAS

IPC: G11C7/00 ,  G11C11/34 ,  G11C13/00 ,  H01L21/18 ,  H01L27/10 ,  H01L27/105

Abstract: The memory device has a memory cell (CM) with a membrane (MB) fixed on a substrate (SB). A deformable part (PDF) is situated at a distance to the substrate and is deformable between two stable mechanical positions corresponding to two logic levels of the memory cell. A deformation unit (MDF) is deforms the membrane. A detection unit (MDT) detects the logic level of the memory cell. Independent claims are also included for the following: (a) an integrated circuit (b) a method of controlling a logic level of a memory cell.