公开(公告)号：JP2001185715A

公开(公告)日：2001-07-06

申请号：JP2000332258

申请日：2000-10-31

Applicant: ST MICROELECTRONICS SA

Inventor： AURIEL GERARD ,  CORNIBERT LAURENT

IPC: H01L29/74 ,  H01L21/225 ,  H01L21/331 ,  H01L21/332 ,  H01L21/76 ,  H01L21/761 ,  H01L21/763 ,  H01L29/06 ,  H01L29/739 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a vertical power element in which the thickness of layer that determines the breakdown voltage of the element is optimized. SOLUTION: In a method of manufacturing the vertical power element on a silicon wafer, a second-conductivity lightly-doped epitaxial layer having such a thickness that can withstand the maximum voltage impressed upon the power element during operation is formed on the upper surface of a first-conductivity heavily-doped substrate and at least one area corresponding to the power element is divided by insulating walls in the wafer. The insulating walls are formed by forming trenches by etching the epitaxial layer and diffusing a first- conductivity dopant having a high doping level into the wafer from the trenches.

公开(公告)号：DE60035246D1

公开(公告)日：2007-08-02

申请号：DE60035246

申请日：2000-11-02

Applicant: ST MICROELECTRONICS SA

Inventor： AURIEL GERARD ,  CORNIBERT LAURENT

IPC: H01L21/763 ,  H01L29/74 ,  H01L21/225 ,  H01L21/331 ,  H01L21/332 ,  H01L21/76 ,  H01L21/761 ,  H01L29/06 ,  H01L29/739 ,  H01L29/78

Abstract: The method for manufacturing a vertical power component on a silicon wafer comprises the following steps: the growth of a weakly doped epitaxial layer (11) of n-type conductivity, where the epitaxial layer has a thickness required to support the maximum voltage applied to the power component in the course of functioning, and the demarcation of a zone corresponding to at least one power component by an insulation wall (16) formed by making a trench (13) through the epitaxial layer and by diffusing a dopant from the trench to obtain a strongly doped p-type conductivity region (14). In a variant of the invention, the trench is constituted by sufficiently close openings so that the diffusion regions of strongly doped p-type conductivity are rejoined; e.g. the openings are of diameter 1-5 micrometre and the mutual distance is 2-10 micrometre. The trench is filled with strongly doped polycrystalline silicon. Parallel insulation walls are formed on the sides of cutting zone separating chips of the same wafer, and the distance between the insulation walls is e.g. 100 micrometre. A power component is made according to the proposed method. As in standard technology, the diffusion is carried out to form a desired component, e.g. a thyristor, comprising doped regions (5,6) of cathodic trigger and cathode respectively, and an annular stop channel (7).

公开(公告)号：FR2800515B1

公开(公告)日：2002-03-29

申请号：FR9914012

申请日：1999-11-03

Applicant: ST MICROELECTRONICS SA

Inventor： AURIEL GERARD ,  CORNIBERT LAURENT

IPC: H01L29/74 ,  H01L21/225 ,  H01L21/331 ,  H01L21/332 ,  H01L21/76 ,  H01L21/761 ,  H01L21/763 ,  H01L29/06 ,  H01L29/739 ,  H01L29/78 ,  H01L29/70

Abstract: The method for manufacturing a vertical power component on a silicon wafer comprises the following steps: the growth of a weakly doped epitaxial layer (11) of n-type conductivity, where the epitaxial layer has a thickness required to support the maximum voltage applied to the power component in the course of functioning, and the demarcation of a zone corresponding to at least one power component by an insulation wall (16) formed by making a trench (13) through the epitaxial layer and by diffusing a dopant from the trench to obtain a strongly doped p-type conductivity region (14). In a variant of the invention, the trench is constituted by sufficiently close openings so that the diffusion regions of strongly doped p-type conductivity are rejoined; e.g. the openings are of diameter 1-5 micrometre and the mutual distance is 2-10 micrometre. The trench is filled with strongly doped polycrystalline silicon. Parallel insulation walls are formed on the sides of cutting zone separating chips of the same wafer, and the distance between the insulation walls is e.g. 100 micrometre. A power component is made according to the proposed method. As in standard technology, the diffusion is carried out to form a desired component, e.g. a thyristor, comprising doped regions (5,6) of cathodic trigger and cathode respectively, and an annular stop channel (7).

公开(公告)号：FR2800515A1

公开(公告)日：2001-05-04

申请号：FR9914012

申请日：1999-11-03

Applicant: ST MICROELECTRONICS SA

Inventor： AURIEL GERARD ,  CORNIBERT LAURENT

IPC: H01L29/74 ,  H01L21/225 ,  H01L21/331 ,  H01L21/332 ,  H01L21/76 ,  H01L21/761 ,  H01L21/763 ,  H01L29/06 ,  H01L29/739 ,  H01L29/78 ,  H01L29/70

Abstract: The method for manufacturing a vertical power component on a silicon wafer comprises the following steps: the growth of a weakly doped epitaxial layer (11) of n-type conductivity, where the epitaxial layer has a thickness required to support the maximum voltage applied to the power component in the course of functioning, and the demarcation of a zone corresponding to at least one power component by an insulation wall (16) formed by making a trench (13) through the epitaxial layer and by diffusing a dopant from the trench to obtain a strongly doped p-type conductivity region (14). In a variant of the invention, the trench is constituted by sufficiently close openings so that the diffusion regions of strongly doped p-type conductivity are rejoined; e.g. the openings are of diameter 1-5 micrometre and the mutual distance is 2-10 micrometre. The trench is filled with strongly doped polycrystalline silicon. Parallel insulation walls are formed on the sides of cutting zone separating chips of the same wafer, and the distance between the insulation walls is e.g. 100 micrometre. A power component is made according to the proposed method. As in standard technology, the diffusion is carried out to form a desired component, e.g. a thyristor, comprising doped regions (5,6) of cathodic trigger and cathode respectively, and an annular stop channel (7).