公开(公告)号：JP2001185715A

公开(公告)日：2001-07-06

申请号：JP2000332258

申请日：2000-10-31

Applicant: ST MICROELECTRONICS SA

Inventor： AURIEL GERARD ,  CORNIBERT LAURENT

IPC: H01L29/74 ,  H01L21/225 ,  H01L21/331 ,  H01L21/332 ,  H01L21/76 ,  H01L21/761 ,  H01L21/763 ,  H01L29/06 ,  H01L29/739 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a vertical power element in which the thickness of layer that determines the breakdown voltage of the element is optimized. SOLUTION: In a method of manufacturing the vertical power element on a silicon wafer, a second-conductivity lightly-doped epitaxial layer having such a thickness that can withstand the maximum voltage impressed upon the power element during operation is formed on the upper surface of a first-conductivity heavily-doped substrate and at least one area corresponding to the power element is divided by insulating walls in the wafer. The insulating walls are formed by forming trenches by etching the epitaxial layer and diffusing a first- conductivity dopant having a high doping level into the wafer from the trenches.

公开(公告)号：DE60035246D1

公开(公告)日：2007-08-02

申请号：DE60035246

申请日：2000-11-02

Applicant: ST MICROELECTRONICS SA

Inventor： AURIEL GERARD ,  CORNIBERT LAURENT

IPC: H01L21/763 ,  H01L29/74 ,  H01L21/225 ,  H01L21/331 ,  H01L21/332 ,  H01L21/76 ,  H01L21/761 ,  H01L29/06 ,  H01L29/739 ,  H01L29/78

Abstract: The method for manufacturing a vertical power component on a silicon wafer comprises the following steps: the growth of a weakly doped epitaxial layer (11) of n-type conductivity, where the epitaxial layer has a thickness required to support the maximum voltage applied to the power component in the course of functioning, and the demarcation of a zone corresponding to at least one power component by an insulation wall (16) formed by making a trench (13) through the epitaxial layer and by diffusing a dopant from the trench to obtain a strongly doped p-type conductivity region (14). In a variant of the invention, the trench is constituted by sufficiently close openings so that the diffusion regions of strongly doped p-type conductivity are rejoined; e.g. the openings are of diameter 1-5 micrometre and the mutual distance is 2-10 micrometre. The trench is filled with strongly doped polycrystalline silicon. Parallel insulation walls are formed on the sides of cutting zone separating chips of the same wafer, and the distance between the insulation walls is e.g. 100 micrometre. A power component is made according to the proposed method. As in standard technology, the diffusion is carried out to form a desired component, e.g. a thyristor, comprising doped regions (5,6) of cathodic trigger and cathode respectively, and an annular stop channel (7).

公开(公告)号：FR2832855A1

公开(公告)日：2003-05-30

申请号：FR0115307

申请日：2001-11-27

Applicant: ST MICROELECTRONICS SA

Inventor： GARDES PASCAL ,  AURIEL GERARD

IPC: H01F17/00 ,  H01F41/04 ,  H01L21/02 ,  H01L23/488 ,  H01L23/535

Abstract: The monolithic circuit includes a substrate (11) on which an inductance is formed. This is achieved by depositing a conducting material on one wall of a spiral channel. The channel may be filled with insulating material. The monolithic circuit includes a substrate (11) on which an inductance is formed. On one surface of the substrate a channel (21) is formed, and this may be in the form of a spiral, extending between a central hole and an outer hole defining the outer end of the spiral. This channel may be formed by laser action. The surface of the channel and that of the end hole is then insulated. Insulation may be achieved in the process by thermal oxidation, whilst the channel itself may alternatively be cut by plasma etching. A conducting material is deposited on at least one wall of the channel, defining a conductive path between the two extreme holes. This conductive spiral forms the inductance. The channel may finally be filled with a further quantity of insulating material.

公开(公告)号：FR2815471A1

公开(公告)日：2002-04-19

申请号：FR0013077

申请日：2000-10-12

Applicant: ST MICROELECTRONICS SA

Inventor： AURIEL GERARD

IPC: H01L29/08 ,  H01L29/747 ,  H01L29/74

Abstract: The vertical four-layer component comprises a thick lightly doped zone (1) of n-type conductivity surrounded by a peripheral wall (2) of p-type conductivity extending verticaly from the rear to the front surface of the component, a highly doped layer (3) of p-type conductivity extending over the rear surfacec of the component, and in addition a lightly doped layer (21) of p-type conductivity extending over the interface between the thick lightly doped zone (1) and the highly doped layer (3). The addition of the lightly doped layer (21) increases the reverse-bias breakdown voltage from 1050 V to 1350 V, that is gives an increase of 25%. In a variant of the device, the vertical semiconductor component constituting a triac comprises a highly doped zone of n-type conductivity formed on the side of the rear surfacce in the highly doped layer (3), and the highly doped layer (21) is interrupted with respect to the additional highly doped zone, which is equipped with short-circuits of emitter. This modification prevents higher threshold current caused by the addition of the lightly doped layer (21), but the breakdown voltage is increased from 1050 V to 1220 V, that is an increase of 15%.

公开(公告)号：FR2800515A1

公开(公告)日：2001-05-04

申请号：FR9914012

申请日：1999-11-03

Applicant: ST MICROELECTRONICS SA

Inventor： AURIEL GERARD ,  CORNIBERT LAURENT

IPC: H01L29/74 ,  H01L21/225 ,  H01L21/331 ,  H01L21/332 ,  H01L21/76 ,  H01L21/761 ,  H01L21/763 ,  H01L29/06 ,  H01L29/739 ,  H01L29/78 ,  H01L29/70

Abstract: The method for manufacturing a vertical power component on a silicon wafer comprises the following steps: the growth of a weakly doped epitaxial layer (11) of n-type conductivity, where the epitaxial layer has a thickness required to support the maximum voltage applied to the power component in the course of functioning, and the demarcation of a zone corresponding to at least one power component by an insulation wall (16) formed by making a trench (13) through the epitaxial layer and by diffusing a dopant from the trench to obtain a strongly doped p-type conductivity region (14). In a variant of the invention, the trench is constituted by sufficiently close openings so that the diffusion regions of strongly doped p-type conductivity are rejoined; e.g. the openings are of diameter 1-5 micrometre and the mutual distance is 2-10 micrometre. The trench is filled with strongly doped polycrystalline silicon. Parallel insulation walls are formed on the sides of cutting zone separating chips of the same wafer, and the distance between the insulation walls is e.g. 100 micrometre. A power component is made according to the proposed method. As in standard technology, the diffusion is carried out to form a desired component, e.g. a thyristor, comprising doped regions (5,6) of cathodic trigger and cathode respectively, and an annular stop channel (7).

公开(公告)号：DE60227899D1

公开(公告)日：2008-09-11

申请号：DE60227899

申请日：2002-10-09

Applicant: ST MICROELECTRONICS SA

Inventor： GARDES PASCAL ,  AURIEL GERARD

IPC: H01F41/04 ,  H01L27/04 ,  H01F17/00 ,  H01L21/02 ,  H01L23/64

Abstract: Fabrication of inductance (10) in monolithic circuit made of silicon substrate (11) with plane upper surface comprises: (a) forming a cavity in substrate following the contour of the inductance to be formed, section of the cavity being deeper than its width; (b) forming porous silicon (27) region at the level of the cavity and oxidizing this region of porous silicon; (c) filling cavity with conducting material. An Independent claim is also included for an inductance formed in a monolithic circuit by this method of fabrication.

公开(公告)号：FR2879348A1

公开(公告)日：2006-06-16

申请号：FR0452963

申请日：2004-12-14

Applicant: ST MICROELECTRONICS SA

Inventor： AURIEL GERARD ,  MERCERON PHILIPPE

IPC: H01L23/60 ,  H01G2/22 ,  H01G4/40 ,  H01L21/02

Abstract: L'invention concerne un dispositif de protection d'au moins un condensateur intégré contre d'éventuelles décharges électrostatiques, comportant deux électrodes conductrices (32, 42) respectivement reliées aux électrodes (21, 51) du condensateur et séparées l'une de l'autre par un intervalle (g) d'air.

公开(公告)号：FR2830670A1

公开(公告)日：2003-04-11

申请号：FR0113055

申请日：2001-10-10

Applicant: ST MICROELECTRONICS SA

Inventor： GARDES PASCAL ,  AURIEL GERARD

IPC: H01L27/04 ,  H01F17/00 ,  H01F41/04 ,  H01L21/02 ,  H01L21/71

Abstract: The monolithic circuit includes a substrate (11) on which an inductance is formed. This is achieved by depositing a conducting material on one wall of a spiral channel. The channel may be filled with insulating material. The monolithic circuit includes a substrate (11) on which an inductance is formed. On one surface of the substrate a channel (21) is formed, and this may be in the form of a spiral, extending between a central hole and an outer hole defining the outer end of the spiral. This channel may be formed by laser action. The surface of the channel and that of the end hole is then insulated. Insulation may be achieved in the process by thermal oxidation, whilst the channel itself may alternatively be cut by plasma etching. A conducting material is deposited on at least one wall of the channel, defining a conductive path between the two extreme holes. This conductive spiral forms the inductance. The channel may finally be filled with a further quantity of insulating material.

公开(公告)号：FR2815471B1

公开(公告)日：2003-02-07

申请号：FR0013077

申请日：2000-10-12

Applicant: ST MICROELECTRONICS SA

Inventor： AURIEL GERARD

IPC: H01L29/08 ,  H01L29/747 ,  H01L29/74

Abstract: The invention concerns a vertical component with a four-layered structure comprising a thick lightly-doped zone ( 1 ) of a first type of conductivity providing the component voltage strength, enclosed with a peripheral wall ( 2 ) of a second type of conductivity extending vertically from one surface to the other of the component, and highly doped layer ( 3 ) of the second type of conductivity extending over the entire rear surface of the component. A lightly-doped layer ( 21 ) of the second type of conductivity extends over the entire surface of the component at the interface between the lightly-doped thick zone of the first type of conductivity and the highly-doped layer of the second type of conductivity.

公开(公告)号：FR2815470A1

公开(公告)日：2002-04-19

申请号：FR0013075

申请日：2000-10-12

Applicant: ST MICROELECTRONICS SA

Inventor： AURIEL GERARD ,  MORILLON BENJAMIN

IPC: H01L21/225 ,  H01L21/24 ,  H01L21/332 ,  H01L29/74 ,  H01L29/72

Abstract: A method for the fabrication of a vertical power component on a silicon chip comprises: (a) growing a weakly doped epitaxial layer (11) of a second type of conductivity on the upper surface of a substrate (10) strongly doped with a first type of conductivity; (b) forming in the substrate the diverse layers of the desired component; (c) and delimiting at least one zone corresponding to at least one power component by an insulating wall formed by depositing a region of aluminum corresponding to the contour of the desired insulating wall and submitting the chip to a temperature gradient leading to a temperature greater than the melting point for aluminum. The epitaxial layer has a thickness adapted to support the maximum voltage of the power component during its operation. An Independent claim is included for a vertical power component fabricated by this method.