Abstract:
The invention concerns a device (UART1) for receiving asynchronous frames starting with a header field (BRK, SYNC, CH1), comprising means (SMI, WU) for standby mode switchover, header field identifying means (SMI), and means (SMI) for switching from standby mode when a valid header field is identified, the standby mode including filtering of at least one signal (DRC) capable of being transmitted by the receiver device during reception of a header field. The invention is in particular applicable to UART circuits present in microcontrollers.
Abstract:
Device (UART1), for received asynchronous frames that start with a header field, comprises means (SM1, WU) for standby mode changeover, header field identifying means (SM1) and means (SM1) for switching from standby mode when a valid header field is identified. Standby mode includes filtering of at least one signal (DRC) capable of being transmitted by the receiver during reception of a header field. The invention also relates to a corresponding method for use with an asynchronous data receiver circuit.
Abstract:
A asynchronous frame receiver includes an input for receiving asynchronous frames. The asynchronous frames include standard characters, and a header that has a data bit length greater than a data bit length of the standard characters. A break character detection unit detects the break character. A standard character processing unit for detecting the standard characters is activated by the break character detection unit based upon the break character being detected.
Abstract:
An asynchronous data transmission device includes a data reception terminal receiving data clocked by a sampling signal in synchronization with a local clock signal. A register is connected to the data reception terminal for receiving the data. A clock deviation measuring circuit is connected to the register for determining a number M of periods of the sampling signal appearing during K periods of a synchronization signal received on the data reception terminal, and for comparing the number M to a tolerance margin defined by a lower threshold and an upper threshold.
Abstract:
Calibration device (CAL) receives a local clock signal from an oscillator (OSC) and applies a correction value to the signal to produce a corrected clock signal (CKC). The correction value is determined based on an external reference signal. The invention also relates to a corresponding integrated circuit, microcontroller and calibration method.
Abstract:
Device (UART1) comprises at least one receive data terminal (RPD) for receipt of data (RDT) and a receive data register (SREG1) which is connected to the receive data terminal. Said receive register is clocked by a strobe (CKS), which is synchronized with a local clock signal (CK). The device further comprises a clock deviation measuring circuit (DMC, B1, B2) which is used to determine the number of strobe periods (M) that appear during K periods of a synchronization signal and to compare the strobe period value with upper and lower thresholds. The invention also relates to a corresponding microcontroller and method for transmission of asynchronous data.
Abstract:
A device for receiving asynchronous frames beginning with a header field, the device including a circuit for switching into a stand-by mode, a circuit for recognizing a header field, and a circuit for leaving the stand-by mode when a valid header field is recognized, the stand-by mode including the filtering of at least one signal likely to be emitted by the receiver device during the reception of a header field. The device is suitable in particular for UART circuits that are present in microcontrollers.
Abstract:
Calibration device (CAL) receives a local clock signal from an oscillator (OSC) and applies a correction value to the signal to produce a corrected clock signal (CKC). The correction value is determined based on an external reference signal. The invention also relates to a corresponding integrated circuit, microcontroller and calibration method.
Abstract:
The receiver accepts frames which comprise standard characters and break characters longer than the standard character. The receiver includes two detectors for the two character types, the standard detector being controlled by the overlength break character detector. The asynchronous frame receiver (UART1) is configured to receive frames which comprise standard characters and, within the header, a break character which is longer than the standard character. The receiver includes a break character detection element (SM1) and a standard character detection element (SM2). The standard character processing element (SM2) is distinct from the break character detection element (SM1) and is activated by the break character detection element when this itself is active. A selection device is provides so that the circuit can operate in two modes, in the first of which the break character detection element is de-activated. In the second mode the break character detection element is activated and thus controlling the standard character detection element.