ASYNCHRONOUS DATA RECEIVER COMPRISING MEANS FOR STANDBY MODE SWITCHOVER
    1.
    发明申请
    ASYNCHRONOUS DATA RECEIVER COMPRISING MEANS FOR STANDBY MODE SWITCHOVER 审中-公开
    包含待机模式开关的手段的异步数据接收器

    公开(公告)号:WO03034247A3

    公开(公告)日:2003-09-25

    申请号:PCT/FR0203479

    申请日:2002-10-11

    CPC classification number: G06F13/385

    Abstract: The invention concerns a device (UART1) for receiving asynchronous frames starting with a header field (BRK, SYNC, CH1), comprising means (SMI, WU) for standby mode switchover, header field identifying means (SMI), and means (SMI) for switching from standby mode when a valid header field is identified, the standby mode including filtering of at least one signal (DRC) capable of being transmitted by the receiver device during reception of a header field. The invention is in particular applicable to UART circuits present in microcontrollers.

    Abstract translation: 本发明涉及用于从头字段(BRK,SYNC,CH1)开始接收异步帧的装置(UART1),包括用于待机模式切换的装置(SMI,WU),头字段识别装置(SMI)和装置(SMI) 用于在识别有效标题字段时从待机模式切换,所述待机模式包括在接收标题字段期间能够由接收机设备发送的至少一个信号(DRC)的过滤。 本发明特别适用于存在于微控制器中的UART电路。

    3.
    发明专利
    未知

    公开(公告)号:DE60202698T2

    公开(公告)日:2006-03-30

    申请号:DE60202698

    申请日:2002-10-11

    Abstract: A asynchronous frame receiver includes an input for receiving asynchronous frames. The asynchronous frames include standard characters, and a header that has a data bit length greater than a data bit length of the standard characters. A break character detection unit detects the break character. A standard character processing unit for detecting the standard characters is activated by the break character detection unit based upon the break character being detected.

    4.
    发明专利
    未知

    公开(公告)号:DE60202697T2

    公开(公告)日:2006-04-06

    申请号:DE60202697

    申请日:2002-10-11

    Abstract: An asynchronous data transmission device includes a data reception terminal receiving data clocked by a sampling signal in synchronization with a local clock signal. A register is connected to the data reception terminal for receiving the data. A clock deviation measuring circuit is connected to the register for determining a number M of periods of the sampling signal appearing during K periods of a synchronization signal received on the data reception terminal, and for comparing the number M to a tolerance margin defined by a lower threshold and an upper threshold.

    6.
    发明专利
    未知

    公开(公告)号:FR2831968B1

    公开(公告)日:2004-06-25

    申请号:FR0114300

    申请日:2001-11-06

    Abstract: Calibration device (CAL) receives a local clock signal from an oscillator (OSC) and applies a correction value to the signal to produce a corrected clock signal (CKC). The correction value is determined based on an external reference signal. The invention also relates to a corresponding integrated circuit, microcontroller and calibration method.

    8.
    发明专利
    未知

    公开(公告)号:DE60203133D1

    公开(公告)日:2005-04-07

    申请号:DE60203133

    申请日:2002-10-11

    Abstract: A device for receiving asynchronous frames beginning with a header field, the device including a circuit for switching into a stand-by mode, a circuit for recognizing a header field, and a circuit for leaving the stand-by mode when a valid header field is recognized, the stand-by mode including the filtering of at least one signal likely to be emitted by the receiver device during the reception of a header field. The device is suitable in particular for UART circuits that are present in microcontrollers.

    Universal asynchronous receiver transceiver includes detector enable use of non-standard length break characters in header information

    公开(公告)号:FR2830955A1

    公开(公告)日:2003-04-18

    申请号:FR0113270

    申请日:2001-10-15

    Abstract: The receiver accepts frames which comprise standard characters and break characters longer than the standard character. The receiver includes two detectors for the two character types, the standard detector being controlled by the overlength break character detector. The asynchronous frame receiver (UART1) is configured to receive frames which comprise standard characters and, within the header, a break character which is longer than the standard character. The receiver includes a break character detection element (SM1) and a standard character detection element (SM2). The standard character processing element (SM2) is distinct from the break character detection element (SM1) and is activated by the break character detection element when this itself is active. A selection device is provides so that the circuit can operate in two modes, in the first of which the break character detection element is de-activated. In the second mode the break character detection element is activated and thus controlling the standard character detection element.

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