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    ASYNCHRONOUS DATA RECEIVER COMPRISING MEANS FOR STANDBY MODE SWITCHOVER
    1.
    发明申请
    ASYNCHRONOUS DATA RECEIVER COMPRISING MEANS FOR STANDBY MODE SWITCHOVER 审中-公开
    包含待机模式开关的手段的异步数据接收器

    公开(公告)号：WO03034247A3

    公开(公告)日：2003-09-25

    申请号：PCT/FR0203479

    申请日：2002-10-11

    Applicant: ST MICROELECTRONICS SA ,  RUAT LUDOVIC ,  KINOWSKI PAUL ,  CZAJOR ALEXANDER

    Inventor： RUAT LUDOVIC ,  KINOWSKI PAUL ,  CZAJOR ALEXANDER

    IPC: G06F13/38

    CPC classification number: G06F13/385

    Abstract: The invention concerns a device (UART1) for receiving asynchronous frames starting with a header field (BRK, SYNC, CH1), comprising means (SMI, WU) for standby mode switchover, header field identifying means (SMI), and means (SMI) for switching from standby mode when a valid header field is identified, the standby mode including filtering of at least one signal (DRC) capable of being transmitted by the receiver device during reception of a header field. The invention is in particular applicable to UART circuits present in microcontrollers.

    Abstract translation: 本发明涉及用于从头字段（BRK，SYNC，CH1）开始接收异步帧的装置（UART1），包括用于待机模式切换的装置（SMI，WU），头字段识别装置（SMI）和装置（SMI） 用于在识别有效标题字段时从待机模式切换，所述待机模式包括在接收标题字段期间能够由接收机设备发送的至少一个信号（DRC）的过滤。 本发明特别适用于存在于微控制器中的UART电路。

    Integrated circuit comprising an active halt mode with low electrical energy consumption, and method for controlling the length of the halt period
    2.
    发明专利
    Integrated circuit comprising an active halt mode with low electrical energy consumption, and method for controlling the length of the halt period 未知

    公开(公告)号：FR2832565A1

    公开(公告)日：2003-05-23

    申请号：FR0114998

    申请日：2001-11-20

    Applicant: ST MICROELECTRONICS SA ,  SGS THOMSON MICROELECTRONICS

    Inventor： RUAT LUDOVIC ,  DEGOT YANNICK ,  BARANWAL DEEPAK

    IPC: G06F1/32 ,  H03F1/32 ,  H03K17/28 ,  H03L7/18

    Abstract: The integrated circuit in the form of a micro-controller (MC) comprises at least one element such as a central processing unit (CPU) timed by a clock signal (CK1) delivered by a first oscillator (OSC1), the means which include the central processing unit (CPU) and a memory program store (MEM) for halting the first oscillator, a timing device (TCT) which is autonomous with respect to the first oscillator, the means which include a control register (CREG) for starting the timing device at the time of halting the first oscillator, and an interruption decoder (ITDEC) for reactivating the first oscillator by the intermediary of the CPU. The ON/OFF input of the first oscillator (OSC1) receives a HALTS signal delivered by the CPU. The timing device (TCT) comprises the means for delivering a reactivation signal (ITCT) by the intermediary of the interruption decoder (ITDEC) in the form of an interruption request signal (IRQ). The autonomous timing device (TCT) is timed by a second oscillator (OSC2) which has a lower electrical consumption than the first oscillator. The first oscillator (OSC1) is a quartz oscillator, and the second oscillator (OSC2) is of type RC. The timing device (TCT) is started by the HALTS signal delivered by the CPU and is a function of at least one control bit such as enable (E) stored in the control register (CREG). The timing device (TCT) comprises the frequency dividers or prescalers (PSC1,PSC2) receiving the second clock signal (CK2), a calibration register (AWUREG) for storing the division factor (N), a calibration circuit (TIMPER) for recalling the divider circuit outside the halt periods of the first oscillator, and a circuit connected to the OFF/ON input of the second oscillator (OSC2) which comprises an OR gate (G1), two AND gates (G2,G3), and an inverter (INV). The method for controlling the length of the halt period in an integrated circuit is implemented by the micro-controller (MC).

    3.
    发明专利
    未知

    公开(公告)号：DE60003315D1

    公开(公告)日：2003-07-17

    申请号：DE60003315

    申请日：2000-07-25

    Applicant: ST MICROELECTRONICS SA

    Inventor： RUAT LUDOVIC ,  FERRAND OLIVIER ,  GAILHARD BRUNO

    IPC: G06K17/00 ,  G06K7/00

    Abstract: A smart card reader includes a housing for receiving a smart card, a microprocessor, and a connector for connecting the microprocessor to the received smart card for establishing communications therebetween. A voltage source provides a power supply voltage to the microprocessor based upon the smart card being received in the housing. The smart card reader further includes a first switch interposed between the voltage source and a power supply terminal of the microprocessor. The first switch is closed when the received smart card is at an end of travel in the housing so that the power supply voltage is provided to the microprocessor, and is opened when the received smart card is no longer at the end of travel in the housing so that the power supply voltage is not provided to the microprocessor.

    Digital timer with rapid trigger, for microprocessor or electronic circuit
    6.
    发明专利
    Digital timer with rapid trigger, for microprocessor or electronic circuit 未知

    公开(公告)号：FR2797120A1

    公开(公告)日：2001-02-02

    申请号：FR9910149

    申请日：1999-07-30

    Applicant: ST MICROELECTRONICS SA

    Inventor： RUAT LUDOVIC ,  FERRAND OLIVIER

    IPC: G04F1/00 ,  H03K21/08 ,  G06G1/04

    Abstract: The digital timer (20) includes a binary counter (21) driven by a counting clock signal (Hc). The counter (21) has a stabilizing time (Ti) after each counting pulse, and means for producing a detection signal (DS2) of a determined value when a counting level (N) is reached. The means for producing the detection signal (DS2) includes: - a cabled logic system (22) arranged or programmed to detect, at the output of the counter (21), a counting value (N-1) of rank immediately lower, relative to the counting sense, at the counting level (N) and to deliver an intermediate signal (DS) of determined value; - means (24) for sampling the intermediate signal (DS1) at the instant (Te) when the counter receives the following counting pulse. The signal (DS1) sampler (24) includes a first synchronous type flip-flop (24) receiving the output of the logic circuit (21) on its data input (D) and the clock signal (Hc) on its clock input (CK). The output of the flip-flop (24) delivers the detection signal (DS2). An Independent Claim is included for a method for transmitting a detection signal when a counting level is reached by the binary counter.

    7.
    发明专利
    未知

    公开(公告)号：DE60202698T2

    公开(公告)日：2006-03-30

    申请号：DE60202698

    申请日：2002-10-11

    Applicant: ST MICROELECTRONICS SA

    Inventor： RUAT LUDOVIC ,  KINOWSKI PAUL ,  CZAJOR ALEXANDER

    IPC: G06F13/38

    Abstract: A asynchronous frame receiver includes an input for receiving asynchronous frames. The asynchronous frames include standard characters, and a header that has a data bit length greater than a data bit length of the standard characters. A break character detection unit detects the break character. A standard character processing unit for detecting the standard characters is activated by the break character detection unit based upon the break character being detected.

    Clock generator for dividing primary frequency by nominated decimal number, comprises a modulation circuit, a modulation distribution circuit and two divisors with down counters
    8.
    发明专利
    Clock generator for dividing primary frequency by nominated decimal number, comprises a modulation circuit, a modulation distribution circuit and two divisors with down counters 未知

    公开(公告)号：FR2845783A1

    公开(公告)日：2004-04-16

    申请号：FR0212794

    申请日：2002-10-15

    Applicant: ST MICROELECTRONICS SA

    Inventor： RUAT LUDOVIC ,  DAVIDESCU DRAGOS

    IPC: G06F1/08 ,  H04L7/00

    Abstract: The programmable clock generator (CKGEN2) is able to deliver a frequency (Fs) equal to a primary frequency (Fo) divided by a nominated decimal number (M,M1,M3) and also provide that the duration of (Ni) impulses is MasteriskNi times the primary period (To). The clock uses a modulation circuit (MODCT), a modulation distribution circuit (DISCT) and two divisors (DIV1,DIV2) Independent claims are also included for the following (1) A circuit for asynchronous transmission/reception of data (UART) which is driven by an over sampled clock signal provided by the programmable clock generator (2) A method for producing a clock signal whose frequency is equal to a primary frequency divided by a decimal number and also for modulating the produced impulses such that the duration of a number of successive impulses is equal to a multiple of the primary period

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