公开(公告)号：JP2001230257A

公开(公告)日：2001-08-24

申请号：JP2001031574

申请日：2001-02-07

Applicant: ST MICROELECTRONICS SA ,  KONINKL PHILIPS ELECTRONICS NV

Inventor： KORDIC SRDJAN ,  TORRES JOAQUIM ,  MOTTE PASCALE ,  DESCOUTS BRIGITTE

IPC: H01L23/52 ,  H01L21/3205 ,  H01L23/522 ,  H01L23/532

Abstract: PROBLEM TO BE SOLVED: To avoid increase of resistivity of a metallic track caused by silicon diffusion to copper. SOLUTION: This process comprises a step for generating at least one metallic track 7 in an inside of a track insulation material 1 at a predetermined metallization level. The generation step of the metallization track 7 comprises an etching step of the track insulation material 1 forming a clearance 4 in the position of the track, a step for depositing a conduction barrier layer 5 in the clearance, a step for filling the clearance with copper, and a step for depositing a silicon nitride layer 8 on the predetermined metallization level. Titanium is deposited in at least a barrier layer between a deposition step of a barrier layer and a filling step of copper. The titanium changes to TiSi2 (60) during silicon diffusion from the silicon nitride layer 8.

公开(公告)号：FR2805084B1

公开(公告)日：2003-09-26

申请号：FR0001801

申请日：2000-02-14

Applicant: ST MICROELECTRONICS SA

Inventor： KORDIC SRDJAN ,  TORRES JOAQUIM ,  MOTTE PASCALE ,  DESCOUTS BRIGITTE

IPC: H01L23/52 ,  H01L21/3205 ,  H01L23/522 ,  H01L23/532

Abstract: A process produces at a predetermined metallization level at least one metal track (7) within an intertrack dielectric material (1). The process includes the steps of etching the intertrack dielectric material (1) so as to form a cavity (4) at the position of the track, depositing a conducting barrier layer (5) in the cavity (4), filling the cavity (4) with copper, and depositing a silicon nitride layer (8) on the predetermined metallization level. Between the barrier layer deposition step and the copper filling step, titanium is deposited on at least part of the barrier layer. This titanium will be transformed into TiSi2 (60) during the diffusion of the silicon from the silicon nitride layer (8).

公开(公告)号：FR2805084A1

公开(公告)日：2001-08-17

申请号：FR0001801

申请日：2000-02-14

Applicant: ST MICROELECTRONICS SA

Inventor： KORDIC SRDJAN ,  TORRES JOAQUIM ,  MOTTE PASCALE ,  DESCOUTS BRIGITTE

IPC: H01L23/52 ,  H01L21/3205 ,  H01L23/522 ,  H01L23/532

Abstract: Integrated circuit production comprises the production of a metal track (7) at the heart of a dielectric inter-track material (1) incorporating an engraving forming a cavity (4), the deposition of a conductive barrier layer (5) in the cavity (4), the filling of the cavity (4) with copper and the deposition of a layer of silicon nitride (8) at a predetermined metallization level. A titanium deposit (6) is realized on at least a part of the barrier layer between the deposition of the barrier layer and the copper filling phases.