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    MANUFACTURING METHOD OF INTEGRATED CIRCUIT
    1.
    发明专利
    MANUFACTURING METHOD OF INTEGRATED CIRCUIT 失效

    公开(公告)号：JP2001230257A

    公开(公告)日：2001-08-24

    申请号：JP2001031574

    申请日：2001-02-07

    Applicant: ST MICROELECTRONICS SA ,  KONINKL PHILIPS ELECTRONICS NV

    Inventor： KORDIC SRDJAN ,  TORRES JOAQUIM ,  MOTTE PASCALE ,  DESCOUTS BRIGITTE

    IPC: H01L23/52 ,  H01L21/3205 ,  H01L23/522 ,  H01L23/532

    Abstract: PROBLEM TO BE SOLVED: To avoid increase of resistivity of a metallic track caused by silicon diffusion to copper. SOLUTION: This process comprises a step for generating at least one metallic track 7 in an inside of a track insulation material 1 at a predetermined metallization level. The generation step of the metallization track 7 comprises an etching step of the track insulation material 1 forming a clearance 4 in the position of the track, a step for depositing a conduction barrier layer 5 in the clearance, a step for filling the clearance with copper, and a step for depositing a silicon nitride layer 8 on the predetermined metallization level. Titanium is deposited in at least a barrier layer between a deposition step of a barrier layer and a filling step of copper. The titanium changes to TiSi2 (60) during silicon diffusion from the silicon nitride layer 8.

    4.
    发明专利
    未知

    公开(公告)号：FR2803092A1

    公开(公告)日：2001-06-29

    申请号：FR9916488

    申请日：1999-12-24

    Applicant: ST MICROELECTRONICS SA

    Inventor： TORRES JOAQUIM ,  GAYET PHILIPPE ,  HAOND MICHEL

    IPC: H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L21/28 ,  H01L23/528

    Abstract: One embodiment of the invention is directed to a method of forming a metallization level of an integrated circuit including the steps of forming metal areas of a metallization level laterally separated by a first insulating layer, removing the first insulating layer, non-conformally depositing a second insulating layer so that gaps can form between neighboring metal areas, or to obtain a porous layer. The removal of the first insulating layer is performed through a mask, to leave in place guard areas of the first insulating layer around the portions of the metal areas intended for being contacted by a via crossing the second insulating layer.

    6.
    发明专利
    未知

    公开(公告)号：FR2805084B1

    公开(公告)日：2003-09-26

    申请号：FR0001801

    申请日：2000-02-14

    Applicant: ST MICROELECTRONICS SA

    Inventor： KORDIC SRDJAN ,  TORRES JOAQUIM ,  MOTTE PASCALE ,  DESCOUTS BRIGITTE

    IPC: H01L23/52 ,  H01L21/3205 ,  H01L23/522 ,  H01L23/532

    Abstract: A process produces at a predetermined metallization level at least one metal track (7) within an intertrack dielectric material (1). The process includes the steps of etching the intertrack dielectric material (1) so as to form a cavity (4) at the position of the track, depositing a conducting barrier layer (5) in the cavity (4), filling the cavity (4) with copper, and depositing a silicon nitride layer (8) on the predetermined metallization level. Between the barrier layer deposition step and the copper filling step, titanium is deposited on at least part of the barrier layer. This titanium will be transformed into TiSi2 (60) during the diffusion of the silicon from the silicon nitride layer (8).

    7.
    发明专利
    未知

    公开(公告)号：FR2803092B1

    公开(公告)日：2002-11-29

    申请号：FR9916488

    申请日：1999-12-24

    Applicant: ST MICROELECTRONICS SA

    Inventor： TORRES JOAQUIM ,  GAYET PHILIPPE ,  HAOND MICHEL

    IPC: H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L21/28 ,  H01L23/528

    Abstract: One embodiment of the invention is directed to a method of forming a metallization level of an integrated circuit including the steps of forming metal areas of a metallization level laterally separated by a first insulating layer, removing the first insulating layer, non-conformally depositing a second insulating layer so that gaps can form between neighboring metal areas, or to obtain a porous layer. The removal of the first insulating layer is performed through a mask, to leave in place guard areas of the first insulating layer around the portions of the metal areas intended for being contacted by a via crossing the second insulating layer.

    Production of integrated circuit comprises incorporating insulating gaseous layer totally separating at least two selected metallized tracks
    8.
    发明专利
    Production of integrated circuit comprises incorporating insulating gaseous layer totally separating at least two selected metallized tracks 未知

    公开(公告)号：FR2823375A1

    公开(公告)日：2002-10-11

    申请号：FR0104820

    申请日：2001-04-09

    Applicant: ST MICROELECTRONICS SA

    Inventor： ARNAL VINCENT ,  TORRES JOAQUIM

    IPC: H01L21/764 ,  H01L21/768 ,  H01L23/522

    Abstract: The production of an integrated circuit incorporating an insulating gaseous layer totally separating at least two selected tracks of a level of metallization of row i (Mi) comprises: (a) realizing the metallization of row I by inserting a sacrificial material (MSi) between the selected tracks at this level; (b) realizing, in the material of the insulating inter-tracks (IMDi+1) separating the tracks of the level of metallization of row i+1 and in the inter-way insulating material (ILDi+1) separating the interconnection contacts at the level of interconnection of row I+1, some shafts (CH) emerging in the sacrificial material; and (c) eliminating the sacrificial material across these shafts. An Independent claim is also included for an integrated circuit incorporating an insulating gaseous layer totally separating at least two tracks of a level of metallization of the circuit (L1, L2).

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