公开(公告)号：DE69713868T2

公开(公告)日：2003-02-27

申请号：DE69713868

申请日：1997-12-16

Applicant: ST MICROELECTRONICS SA

Inventor： DEYGAS OLIVIER ,  HARRAND MICHEL

IPC: G06T9/00

Abstract: The microprocessor has a dedicated circuit which concatenates variable length codes, extracts variable length codes from contiguous codes and calculates a signature from a sequence of bits. The dedicated circuit uses an instruction of two parameters, the first (D) is a group of bits and the second (L) indicates the length of the first. The working register (CAT) contains the concatenation code and supplies a shift register (42) and an OR gate (44). An indicating register (46) indicates free space in the working register (CAT) and a subtracting register produces the difference. A multiplexer (52) takes the output from either the OR gate or the bit to bit gate (54) as required by the subtracting register.

公开(公告)号：DE69713867T2

公开(公告)日：2003-03-13

申请号：DE69713867

申请日：1997-12-16

Applicant: ST MICROELECTRONICS SA

Inventor： DEYGAS OLIVIER ,  HARRAND MICHEL

IPC: G06T9/00

Abstract: The microprocessor has an operator which is dedicated to calculation of a signature. The operator uses two parameters, with the first a word containing a group of bits from the sequence and the second indicating the length of the group of bits. The operator reacts to the instruction by updating a signature register. The updated signature is the remainder from a polynomial division by a polynomial generator. The dedicated operator has XOR-gates arranged in rows and columns. The number of columns corresponds to the size of the signature register and the number of rows to the maximum length of the group of bits. The appropriate row is selected in response to the second parameter and is transferred to the signature register.

公开(公告)号：DE69713868D1

公开(公告)日：2002-08-14

申请号：DE69713868

申请日：1997-12-16

Applicant: ST MICROELECTRONICS SA

Inventor： DEYGAS OLIVIER ,  HARRAND MICHEL

IPC: G06T9/00

Abstract: The microprocessor has a dedicated circuit which concatenates variable length codes, extracts variable length codes from contiguous codes and calculates a signature from a sequence of bits. The dedicated circuit uses an instruction of two parameters, the first (D) is a group of bits and the second (L) indicates the length of the first. The working register (CAT) contains the concatenation code and supplies a shift register (42) and an OR gate (44). An indicating register (46) indicates free space in the working register (CAT) and a subtracting register produces the difference. A multiplexer (52) takes the output from either the OR gate or the bit to bit gate (54) as required by the subtracting register.

公开(公告)号：DE69713867D1

公开(公告)日：2002-08-14

申请号：DE69713867

申请日：1997-12-16

Applicant: ST MICROELECTRONICS SA

Inventor： DEYGAS OLIVIER ,  HARRAND MICHEL

IPC: G06T9/00

Abstract: The microprocessor has an operator which is dedicated to calculation of a signature. The operator uses two parameters, with the first a word containing a group of bits from the sequence and the second indicating the length of the group of bits. The operator reacts to the instruction by updating a signature register. The updated signature is the remainder from a polynomial division by a polynomial generator. The dedicated operator has XOR-gates arranged in rows and columns. The number of columns corresponds to the size of the signature register and the number of rows to the maximum length of the group of bits. The appropriate row is selected in response to the second parameter and is transferred to the signature register.