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公开(公告)号：FR2789247A1
公开(公告)日：2000-08-04
申请号：FR9900930
申请日：1999-01-28
Applicant: ST MICROELECTRONICS SA
Inventor： PLESSIER BERNARD , DO TIEN DUNG
Abstract: System has synchronizing cells (7,8) clocked by a primary clock signal (H0) and outputting secondary clock signals (H1,H2) as requested by validation signals (V1,V2), which respectively activate first and second modules. The cells have means (10) for locking each signal (V1) associated with means (11,12) for equalizing the secondary clock signal (H1) time period and for coordinating signals (H1,H2).
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公开(公告)号：FR2789247B1
公开(公告)日：2004-10-15
申请号：FR9900930
申请日：1999-01-28
Applicant: ST MICROELECTRONICS SA
Inventor： PLESSIER BERNARD , DO TIEN DUNG
Abstract: In the field of systems for the synchronization of modular electronic circuits, a system is provided for the coordinated activation of the modules. This system includes synchronization cells that have their pace set by a primary clock signal and deliver secondary clock signals controlled intermittently by the enabling signals to respectively activate the modules. The cells lock the state of each enabling signal associated with a regulator for regulating the periodicity of the change in state of each secondary clock signal and coordinating the changes in states of the secondary clock signals with one another. The system can be advantageously applied to electronic circuits having very high frequency data processing modules, especially those providing for the multiplexing of the transmissions of data carried out by each module.
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