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    2.
    发明专利
    未知

    公开(公告)号：FR2821208B1

    公开(公告)日：2003-04-11

    申请号：FR0102347

    申请日：2001-02-21

    Applicant: ST MICROELECTRONICS SA

    Inventor： CORONEL PHILIPPE ,  LEVERD FRANCOIS ,  FERREIRA PAUL

    IPC: H01L21/60 ,  H01L21/768 ,  H01L23/52 ,  H01L21/8239

    Abstract: The invention relates to a process for protection of the grid of a transistor in an integrated circuit for production of a local interconnection pad straddling over the grid and the silicon substrate on which it is formed. The process consists of applying a double dielectric-conducting layer on the transistor grid into which a polysilicon layer is added in order to use the selectivity principle, which is large considering the etching of polysilicon with respect to the oxide in which the local interconnection pad is formed. Furthermore, with the process according to the invention, a silicidation treatment can be applied beforehand on the active areas of the transistor and the grid.

    3.
    发明专利
    未知

    公开(公告)号：FR2842944A1

    公开(公告)日：2004-01-30

    申请号：FR0209347

    申请日：2002-07-23

    Applicant: ST MICROELECTRONICS SA

    Inventor： FERREIRA PAUL ,  CORONEL PHILIPPE

    IPC: H01L21/033 ,  H01L21/311 ,  H01L21/60 ,  H01L23/50 ,  H01L21/265

    Abstract: The method for making contact openings in the upper surface of an integrated circuit in regions between higher zones applies in two cases, when the higher zones are well-spaced with noncritical openings (41), and when the higher zones are in proximity with critical openings (42). The method comprises the steps of covering the upper surface structure with a first protection layer (20); making the noncritical openings (41) in the first protection layer; covering the structure with the secodn protection layer; oblique irradiation carried out so that the second protection layer is not irradiated at the bottom of regions between two higher zones; eliminating the nonirradiated parts of the second protection layer; eliminating the parts of the first protection layer at locations where the second protection layer has been eliminated; and eliminating the irradiated parts of the second protection layer. The first protection layer (20) is of silicon nitride. The second protection layer is of polycrystalline silicon. The irradiation process is that of boron implanting. The oblique irradiation is carried out at an angle in the range 45-60 deg. The higher zones correspond to the gates (3) of MOS transistors. The zones susceptible of contact, that is a short-circuit, are covered with a metal silicide. The step of making the noncritical openings (41) comprises the steps of covering the structure with a planarization layer; eliminating the planarization layer at locations of the openings; etching the openings in the first protection layer; and eliminating the planarization layer. The planarization layer is of resin.

    5.
    发明专利
    未知

    公开(公告)号：FR2821208A1

    公开(公告)日：2002-08-23

    申请号：FR0102347

    申请日：2001-02-21

    Applicant: ST MICROELECTRONICS SA

    Inventor： CORONEL PHILIPPE ,  LEVERD FRANCOIS ,  FERREIRA PAUL

    IPC: H01L21/60 ,  H01L21/768 ,  H01L23/52 ,  H01L21/8239

    Abstract: The invention relates to a process for protection of the grid of a transistor in an integrated circuit for production of a local interconnection pad straddling over the grid and the silicon substrate on which it is formed. The process consists of applying a double dielectric-conducting layer on the transistor grid into which a polysilicon layer is added in order to use the selectivity principle, which is large considering the etching of polysilicon with respect to the oxide in which the local interconnection pad is formed. Furthermore, with the process according to the invention, a silicidation treatment can be applied beforehand on the active areas of the transistor and the grid.

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