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公开(公告)号：DE60015882T2
公开(公告)日：2005-12-08
申请号：DE60015882
申请日：2000-09-08
Applicant: ST MICROELECTRONICS SA
Inventor： GAILHARD BRUNO
Abstract: A regulated voltage (Vreg) is delivered by a regulating capacitor (Creg), which is connected to a supply (Vdd) through a main switch (SW1) and a ballast switch (SW2) with resistance (R2). A regulating unit control (11) closes the ballast switch and opens the main switch when the regulated voltage is less than a first lower reference (Vref2). At higher voltages the main switch regulates on the higher reference voltage (Vref1).
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公开(公告)号：DE60015882D1
公开(公告)日：2004-12-23
申请号：DE60015882
申请日：2000-09-08
Applicant: ST MICROELECTRONICS SA
Inventor： GAILHARD BRUNO
Abstract: A regulated voltage (Vreg) is delivered by a regulating capacitor (Creg), which is connected to a supply (Vdd) through a main switch (SW1) and a ballast switch (SW2) with resistance (R2). A regulating unit control (11) closes the ballast switch and opens the main switch when the regulated voltage is less than a first lower reference (Vref2). At higher voltages the main switch regulates on the higher reference voltage (Vref1).
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公开(公告)号：FR2832819A1
公开(公告)日：2003-05-30
申请号：FR0115259
申请日：2001-11-26
Applicant: ST MICROELECTRONICS SA
Inventor： FERRAND OLIVIER , GAILHARD BRUNO
Abstract: The current source has a circuit with a branch (b1) fixing a reference voltage (V1), a branch (b2) fixing a reference current and a branch (b3) supplying a current obtained from current mirror (M2,M3), with a second current mirror (M1,M2) that is connected to ground through resistances (R1,R2) in series with transistors (Q) to compensate current variations by selecting resistance values.
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公开(公告)号：FR2816136A1
公开(公告)日：2002-05-03
申请号：FR0013897
申请日：2000-10-30
Applicant: ST MICROELECTRONICS SA
Inventor： GAILHARD BRUNO , FERRAND OLIVIER
Abstract: The generator comprises an oscillator producing a clock signal (CKHF) on the basis of N decoded control signals SD(1), SD(2), ..., SD(N) received from a comparator and obtained by comparing the period of the clock signal to a desired period which is e.g. a multiple of a reference signal period. The oscillator (40) comprises N=2n components C(0), C(1), ..., C(N-1) connected in series, where the low-weight component C(0) delivers the clock signal. At least one component (C(i) of weight i comprises two inputs (a,b), two outputs (c,d), and three branches: the first branch (a-d) contains an interrupter INT(i+1) which is closed when the control signal SD(i+1) is active; the second branch (a-c) contains an interrupter INTA(i) and at least one, in particular two inverters connected in series; the third branch (b-d) contains an interrupter INTB(i); the interrupters INTA(i) and INTB(i) are open when the control signal SD(i) is active. The low-weight component C(0) comprises an odd number (NB) of inverters, where the number is greater than or equal to 1. The component C(i) of weight i greater than 1 comprises an even number (NC) of inverters connected in series in branch (a-c) and/or in branch (b-d); or odd numbers of inverters in branches (a-c) and (b-d). The branches (a-d) are identical and contain the same number of inverters. The components C(i) of weight i in the range from 1 to N-1 are identical. The generator comprises a comparator which receives the clock signal (CKIHF) and delivers the control number with n bits in the form N=2n of binary signals which are decoded; the control number is increased/decreased if the period of the clock signal is below/above the desired period, and remains constant otherwise.
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公开(公告)号：FR2798018B1
公开(公告)日：2002-02-15
申请号：FR9911138
申请日：1999-08-31
Applicant: ST MICROELECTRONICS SA
Inventor： GAILHARD BRUNO
Abstract: A power-on-reset circuit for delivering a power-on-reset pulse when a supply voltage ramps up from zero to a predetermined voltage includes a pull-down circuit portion for connecting an output node of the power-on-reset circuit to ground when the supply voltage reaches a predetermined upper threshold voltage and a pull-up circuit portion for connecting the output node to the supply voltage when the supply voltage reaches a predetermined upper threshold voltage. The pull-up circuit portion includes a transistor whose gate is polarized by a reference voltage taken at the terminals of a precision resistance traversed by a current delivered by a current generator, where the current is preferably a band-gap current proportional to the temperature of the circuit. The power-on-reset circuit is particularly suitable for microprocessors.
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Patent Agency Ranking
公开(公告)号：FR2797070A1
公开(公告)日：2001-02-02
申请号：FR9910150
申请日：1999-07-30
Applicant: ST MICROELECTRONICS SA
Inventor： RUAT LUDOVIC , FERRAND OLIVIER , GAILHARD BRUNO
Abstract: The invention concerns a smart card reader (20) comprising a housing for receiving the card, a microprocessor (30), means for connecting the microprocessor to the smart card inserted in the housing and a voltage source (21). The invention is characterised in that the microprocessor (30) is electrically powered by the voltage source (21) via a switch (24) which is normally open, and is arranged to be closed when the card is completely inserted in the housing. The invention is particularly applicable to viewer card readers powered by an electric battery.
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公开(公告)号：FR2816134A1
公开(公告)日：2002-05-03
申请号：FR0013901
申请日：2000-10-30
Applicant: ST MICROELECTRONICS SA
Inventor： GAILHARD BRUNO , FERRAND OLIVIER
Abstract: The generator (30) comprises a frequency divider (32), a phase comparator (34) delivering the control signals (UP, DOWN), a sampler (35), a voltage generator (36) delivering the control voltage (VCK), and an oscillator (30) delivering the high-frequency clock signal (CKHF) whose frequency depends on the control voltage; the devices are connected in series, and the output of the oscillator is connected to the input of the frequency divider forming the phase-locked loop, and also to the clock input of sampler. The precision of generator can be substantially increased by connecting a separate oscillator (40) to the clock input of sampler. The sampler (35) delivers the sampled control signals (UPech, DOWNech) to the voltage generator (36), which delivers the control voltage (VCK) as a function of the sampled control signals. The sampler (35) contains a counter receiving a validation signal and delivering a sampling signal when the number of counted pulses reaches a set number, and the counter is reset when it reaches another set number; two logic gates receiving the sampling signal on one input and each one of the control signals on the other input, and delivering the samples control signals; and a third logic gate receiving the two control signals and delivering the validation signal. The period of sampling signal is less than or equal to the desired period.
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公开(公告)号：FR2816075A1
公开(公告)日：2002-05-03
申请号：FR0013903
申请日：2000-10-30
Applicant: ST MICROELECTRONICS SA
Inventor： GAILHARD BRUNO , FERRAND OLIVIER
Abstract: A high frequency clock signal generator (20) includes a frequency divider (22) giving a low frequency signal (CKHFN), a unit (24) which compares the frequency divider signal with a reference signal (CKBF) and an oscillator (26) providing the high frequency clock signal (CKFH). An initialization circuit (28) provides an initialization signal (RESET) for each reference signal (CKBF) rising front thus synchronizing the low frequency and reference signals
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公开(公告)号：FR2797070B1
公开(公告)日：2001-09-28
申请号：FR9910150
申请日：1999-07-30
Applicant: ST MICROELECTRONICS SA
Inventor： RUAT LUDOVIC , FERRAND OLIVIER , GAILHARD BRUNO
Abstract: A smart card reader includes a housing for receiving a smart card, a microprocessor, and a connector for connecting the microprocessor to the received smart card for establishing communications therebetween. A voltage source provides a power supply voltage to the microprocessor based upon the smart card being received in the housing. The smart card reader further includes a first switch interposed between the voltage source and a power supply terminal of the microprocessor. The first switch is closed when the received smart card is at an end of travel in the housing so that the power supply voltage is provided to the microprocessor, and is opened when the received smart card is no longer at the end of travel in the housing so that the power supply voltage is not provided to the microprocessor.
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公开(公告)号：FR2816075B1
公开(公告)日：2004-05-28
申请号：FR0013903
申请日：2000-10-30
Applicant: ST MICROELECTRONICS SA
Inventor： GAILHARD BRUNO , FERRAND OLIVIER
Abstract: An integrated circuit includes a generator for providing a clock signal from a reference signal. The generator, which is of the phase-locked loop type, includes a frequency divider and a phase comparator connected together. A reset circuit is connected to the frequency divider and to the phase comparator for providing a reset signal thereto at each leading edge of the reference signal for synchronizing a low-frequency signal with the reference signal.
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