公开(公告)号：FR2838840B1

公开(公告)日：2005-04-01

申请号：FR0205042

申请日：2002-04-23

Applicant: ST MICROELECTRONICS SA

Inventor： GANIVET FILIPE ,  GIOVINAZZI THIERRY ,  LA ROSA FRANCESCO

IPC: G05F3/26 ,  G11C5/14 ,  G11C16/30 ,  H03K17/30

Abstract: The comparator (COMP) delivers two different outputs depending on which of the input voltages (V1,V2) is higher. The comparator has two PMOS transistors (TP1,TP2) in a current mirror circuit, with the first having its source connected to the first input (V1,Vcc) and the second having its source connected to the second input. The comparator output is connected to the drain of one transistor.

公开(公告)号：FR2838861A1

公开(公告)日：2003-10-24

申请号：FR0205041

申请日：2002-04-23

Applicant: ST MICROELECTRONICS SA

Inventor： GANIVET FILIPE ,  GIOVINAZZI THIERRY ,  LA ROSA FRANCESCO

IPC: G11C16/30

Abstract: The memory store (MEM2) containing a memory array (MA) which comprises memory cells, also comprises a voltage supply managing circuit (PSMC) with a line (20) for distributing an internal supply voltage (Vps1) connected on one hand to a terminal (21) of an external voltage supply (Vcc) by the intermediary of a diode or a diode-simulation circuit (SDC), and on the other hand to a step-up voltage circuit (PMP3). The voltage supply managing circuit (PSMC) also comprises a regulator (REG3) for triggering the step-up voltage circuit (PMP3) when the internal supply voltage (Vps1) falls below a determined threshold (Vmin3), a slope generator (RAMPGEN) for progressively applying a higher voltage (Vpp), a gate generator (CGGEN) for generating the gate control voltage (Vcg), and a secondary voltage supply managing circuit (SPSMC) which comprises switches (SW1,SW2) in the form of MOS transistors, and inverters (11,12) connected to the gates of transistors. The internal supply voltage (Vps1) is maintained in the neighbourhood of the threshold (Vmin3) when the external supply voltage (Vcc) is too weak, at least during the reading of the memory cells when the diode-simulation circuit (SDC) remains blocked, that is in the off state. The threshold voltage (Vmin3) is greater or equal to the sum of the read voltage (Vread), or the drain polarization voltage (Vpol), and the threshold voltage (Vt) of MOS transistor. The step-up voltage circuit (PMP3) is for carrying the internal supply voltage (Vps1) to a higher voltage (Vpp) required for the erasing of the programming of memory cells. The step-up voltage circuit (PMP3) is of type charge pump. The memory store comprises a row decoder (RDEC) whose supply terminal (T1) is connected to the distribution line (20) of voltage (Vps1), and a column decoder (CDEC) whose supply terminal (T2) is connected to the secondary voltage (Vps2). The diode-simulation circuit (SDC) comprises a supply interrupter with a low voltage drop in the form of MOS transistor, and the means for controlling the interrupter with a low voltage drop in the form of MOS transistor, and the means for controlling the interrupter in the form of a differential circuit for comparing the external supply voltage and the internal supply voltage. A method (claimed) for managing the internal voltage supply is implemented by the device as claimed.

公开(公告)号：DE60142801D1

公开(公告)日：2010-09-23

申请号：DE60142801

申请日：2001-06-15

Applicant: ST MICROELECTRONICS SA

Inventor： GIOVINAZZI THIERRY ,  GANIVET FILIPE

IPC: G11C5/06 ,  G11C7/00

公开(公告)号：DE60311537D1

公开(公告)日：2007-03-22

申请号：DE60311537

申请日：2003-04-17

Applicant: ST MICROELECTRONICS SA

Inventor： GANIVET FILIPE ,  LA ROSA FRANCESCO ,  GIOVINAZZI THIERRY

IPC: G11C16/30

Abstract: The memory store (MEM2) containing a memory array (MA) which comprises memory cells, also comprises a voltage supply managing circuit (PSMC) with a line (20) for distributing an internal supply voltage (Vps1) connected on one hand to a terminal (21) of an external voltage supply (Vcc) by the intermediary of a diode or a diode-simulation circuit (SDC), and on the other hand to a step-up voltage circuit (PMP3). The voltage supply managing circuit (PSMC) also comprises a regulator (REG3) for triggering the step-up voltage circuit (PMP3) when the internal supply voltage (Vps1) falls below a determined threshold (Vmin3), a slope generator (RAMPGEN) for progressively applying a higher voltage (Vpp), a gate generator (CGGEN) for generating the gate control voltage (Vcg), and a secondary voltage supply managing circuit (SPSMC) which comprises switches (SW1,SW2) in the form of MOS transistors, and inverters (11,12) connected to the gates of transistors. The internal supply voltage (Vps1) is maintained in the neighbourhood of the threshold (Vmin3) when the external supply voltage (Vcc) is too weak, at least during the reading of the memory cells when the diode-simulation circuit (SDC) remains blocked, that is in the off state. The threshold voltage (Vmin3) is greater or equal to the sum of the read voltage (Vread), or the drain polarization voltage (Vpol), and the threshold voltage (Vt) of MOS transistor. The step-up voltage circuit (PMP3) is for carrying the internal supply voltage (Vps1) to a higher voltage (Vpp) required for the erasing of the programming of memory cells. The step-up voltage circuit (PMP3) is of type charge pump. The memory store comprises a row decoder (RDEC) whose supply terminal (T1) is connected to the distribution line (20) of voltage (Vps1), and a column decoder (CDEC) whose supply terminal (T2) is connected to the secondary voltage (Vps2). The diode-simulation circuit (SDC) comprises a supply interrupter with a low voltage drop in the form of MOS transistor, and the means for controlling the interrupter with a low voltage drop in the form of MOS transistor, and the means for controlling the interrupter in the form of a differential circuit for comparing the external supply voltage and the internal supply voltage. A method (claimed) for managing the internal voltage supply is implemented by the device as claimed.

公开(公告)号：FR2838840A1

公开(公告)日：2003-10-24

申请号：FR0205042

申请日：2002-04-23

Applicant: ST MICROELECTRONICS SA

Inventor： GANIVET FILIPE ,  GIOVINAZZI THIERRY ,  LA ROSA FRANCESCO

IPC: G05F3/26 ,  G11C5/14 ,  G11C16/30 ,  H03K17/30

Abstract: The comparator (COMP) delivers two different outputs depending on which of the input voltages (V1,V2) is higher. The comparator has two PMOS transistors (TP1,TP2) in a current mirror circuit, with the first having its source connected to the first input (V1,Vcc) and the second having its source connected to the second input. The comparator output is connected to the drain of one transistor.