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公开(公告)号：FR2822606B1
公开(公告)日：2003-08-08
申请号：FR0103794
申请日：2001-03-21
Applicant: ST MICROELECTRONICS SA
Inventor： GARCIA LUC
Abstract: The circuit comprises two identical multiplication cells (C1,C2), each with two inputs (E1,E2) and an output (S), and an addition circuit (ADD), for adding the output signals of two cells in order to obtain an output signal devoid of a direct component. The input sinusoidal signals (S1(t), S2(t)) are applied to the respective inputs of the first cell (C1), and crossed to the inputs of the second cell (C2). The output signal (O1(t),O2(t)) of the two cells are added to give the output signal (O(t)) of the circuit without the direct component. The two multiplication cells (C1,C2) are paired and implemented in the same integrated circuit. Each multiplication cell (C1,C2) contains two phase-delay elements (Phase SIMILAR F1, Phase phi 2), one for each input, and an ideal multiplication circuit. The output signal (O(t)) is sinusoidal, has the frequency doubled, the amplitude equal to the product of two amplitudes, and the direct components cancelled out by addition.
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公开(公告)号：FR2822616B1
公开(公告)日：2003-08-01
申请号：FR0103788
申请日：2001-03-21
Applicant: ST MICROELECTRONICS SA
Inventor： JOISSON MARC , GARCIA LUC , GENS MARC
IPC: H04L27/156 , H04L27/14
Abstract: A receiver of a frequency-modulated signal is provided. The receiver includes a frequency-transposition unit for lowering the frequency of the frequency-modulated signal, and a digital demodulator for regenerating a digital signal from the frequency-transposed signal. The frequency-transposition unit includes a local oscillator for generating a local oscillator signal used in lowering the frequency of the frequency-modulated signal. The frequency-transposed signal is sampled in the digital demodulator at the rate of a sampling signal, and the sampling signal is generated by the local oscillator of the frequency-transposition unit. In a preferred embodiment, the local oscillator includes at least one frequency-divider circuit that delivers the sampling signal. Also provided is a method for regenerating a digital signal from a frequency-modulated signal.
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Patent Agency Ranking
公开(公告)号：FR2825205A1
公开(公告)日：2002-11-29
申请号：FR0106766
申请日：2001-05-23
Applicant: ST MICROELECTRONICS SA
Inventor： JOISSON MARC , GARCIA LUC , LEVEQUE SEBASTIEN
IPC: H04L27/156 , H04B1/18
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公开(公告)号：FR2822616A1
公开(公告)日：2002-09-27
申请号：FR0103788
申请日：2001-03-21
Applicant: ST MICROELECTRONICS SA
Inventor： JOISSON MARC , GARCIA LUC , GENS MARC
IPC: H04L27/156 , H04L27/14
Abstract: An integrated circuit FSK receiver digitally demodulates the intermediate frequency with a sampling signal (ECH) from the frequency conversion module (12) local oscillator (14) phase locked loop first division circuit (20)
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公开(公告)号：DE60220572D1
公开(公告)日：2007-07-26
申请号：DE60220572
申请日：2002-03-20
Applicant: ST MICROELECTRONICS SA
Inventor： JOISSON MARC , GARCIA LUC , GENS MARC
IPC: H04L27/14 , H04L27/152 , H04L27/156
Abstract: A receiver of a frequency-modulated signal is provided. The receiver includes a frequency-transposition unit for lowering the frequency of the frequency-modulated signal, and a digital demodulator for regenerating a digital signal from the frequency-transposed signal. The frequency-transposition unit includes a local oscillator for generating a local oscillator signal used in lowering the frequency of the frequency-modulated signal. The frequency-transposed signal is sampled in the digital demodulator at the rate of a sampling signal, and the sampling signal is generated by the local oscillator of the frequency-transposition unit. In a preferred embodiment, the local oscillator includes at least one frequency-divider circuit that delivers the sampling signal. Also provided is a method for regenerating a digital signal from a frequency-modulated signal.
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公开(公告)号：FR2876233A1
公开(公告)日：2006-04-07
申请号：FR0452279
申请日：2004-10-06
Applicant: ST MICROELECTRONICS SA
Inventor： BELVEZE FABRICE , GARCIA LUC
Abstract: L'invention concerne un filtre (20) destiné à recevoir un signal à temps discret à une fréquence d'horloge d'échantillonnage, comprenant un nombre déterminé, supérieur à 2, de modules de filtrage (Fi), chaque module de filtrage comprenant des condensateurs de tête (CHi,0, CHi,1, CHi,2, CHi,3) en nombre égal au nombre déterminé, montés en parallèle entre une borne d'entrée et la borne d'un condensateur d'intégration (CIi,0) ; et des moyens (SWi,0, SWi,2, SWi,4, SWi,6, SWi,1, SWi,3, SWi,5, SWi,7) pour relier, au cours de cycles d'horloge successifs en nombre égal au nombre déterminé, successivement chaque condensateur de tête à la borne d'entrée, et pour alors relier simultanément les condensateurs de tête au condensateur d'intégration, et dans lequel les cycles d'horloge successifs au cours desquels les condensateurs de tête d'un module de filtrage sont reliés à la borne d'entrée sont décalés d'un cycle d'horloge d'un module de filtrage au suivant.
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公开(公告)号：FR2822606A1
公开(公告)日：2002-09-27
申请号：FR0103794
申请日：2001-03-21
Applicant: ST MICROELECTRONICS SA
Inventor： GARCIA LUC
Abstract: The circuit comprises two identical multiplication cells (C1,C2), each with two inputs (E1,E2) and an output (S), and an addition circuit (ADD), for adding the output signals of two cells in order to obtain an output signal devoid of a direct component. The input sinusoidal signals (S1(t), S2(t)) are applied to the respective inputs of the first cell (C1), and crossed to the inputs of the second cell (C2). The output signal (O1(t),O2(t)) of the two cells are added to give the output signal (O(t)) of the circuit without the direct component. The two multiplication cells (C1,C2) are paired and implemented in the same integrated circuit. Each multiplication cell (C1,C2) contains two phase-delay elements (Phase SIMILAR F1, Phase phi 2), one for each input, and an ideal multiplication circuit. The output signal (O(t)) is sinusoidal, has the frequency doubled, the amplitude equal to the product of two amplitudes, and the direct components cancelled out by addition.
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