公开(公告)号：FR2828579B1

公开(公告)日：2004-01-30

申请号：FR0110768

申请日：2001-08-13

Applicant: ST MICROELECTRONICS SA

Inventor： GARDES PASCAL

IPC: H01L21/68 ,  H01L21/30

Abstract: A thin silicon wafer is handled by fastening external layer of wafer and gluing layer of support wafer by direct gluing, and processing the wafer to form circuits. A protection layer is deposited on the wafer surface, which is not glued to the support wafer. The material forming the external layer of the water and the gluing layer of the support wafer are removed by an etch process. Handling of thin silicon wafer (20) includes successively forming on a surface of wafer a first protection layer (21), first etch stop layer (22), and external layer (23, 26). A gluing layer of the same material the external layer of the wafer is formed on a surface of the support wafer. The support wafer includes pads having upper portions that are planar and coplanar. The external layer of the wafer and gluing layer of the support wafer are fastened by direct gluing. The wafer is processed to form circuits. A second protection layer (24) is deposited on the wafer surface, which is not glued to the support wafer (30). The material forming the external layer of the water and the gluing layer of the support wafer are removed by an etch process.

公开(公告)号：FR2828579A1

公开(公告)日：2003-02-14

申请号：FR0110768

申请日：2001-08-13

Applicant: ST MICROELECTRONICS SA

Inventor： GARDES PASCAL

IPC: H01L21/68 ,  H01L21/30

Abstract: A thin silicon wafer is handled by fastening external layer of wafer and gluing layer of support wafer by direct gluing, and processing the wafer to form circuits. A protection layer is deposited on the wafer surface, which is not glued to the support wafer. The material forming the external layer of the water and the gluing layer of the support wafer are removed by an etch process. Handling of thin silicon wafer (20) includes successively forming on a surface of wafer a first protection layer (21), first etch stop layer (22), and external layer (23, 26). A gluing layer of the same material the external layer of the wafer is formed on a surface of the support wafer. The support wafer includes pads having upper portions that are planar and coplanar. The external layer of the wafer and gluing layer of the support wafer are fastened by direct gluing. The wafer is processed to form circuits. A second protection layer (24) is deposited on the wafer surface, which is not glued to the support wafer (30). The material forming the external layer of the water and the gluing layer of the support wafer are removed by an etch process.

公开(公告)号：FR2830123A1

公开(公告)日：2003-03-28

申请号：FR0112383

申请日：2001-09-26

Applicant: ST MICROELECTRONICS SA

Inventor： GARDES PASCAL

IPC: H01L29/78 ,  H01L21/00 ,  H01L21/762 ,  H01L21/84 ,  H01L29/06 ,  H01L29/40 ,  H01L21/71 ,  H01L23/58

Abstract: A conductive plate is formed simultaneously with the lateral wall on a protective layer (6) of a semiconductor substrate (1). The conductive wall which is in contact with the peripheral region (8) is extended towards the well (5) above the limit between the peripheral region and the substrate. An Independent claim is also included for a discrete high voltage component.

公开(公告)号：DE60227899D1

公开(公告)日：2008-09-11

申请号：DE60227899

申请日：2002-10-09

Applicant: ST MICROELECTRONICS SA

Inventor： GARDES PASCAL ,  AURIEL GERARD

IPC: H01F41/04 ,  H01L27/04 ,  H01F17/00 ,  H01L21/02 ,  H01L23/64

Abstract: Fabrication of inductance (10) in monolithic circuit made of silicon substrate (11) with plane upper surface comprises: (a) forming a cavity in substrate following the contour of the inductance to be formed, section of the cavity being deeper than its width; (b) forming porous silicon (27) region at the level of the cavity and oxidizing this region of porous silicon; (c) filling cavity with conducting material. An Independent claim is also included for an inductance formed in a monolithic circuit by this method of fabrication.

公开(公告)号：FR2911993A1

公开(公告)日：2008-08-01

申请号：FR0752981

申请日：2007-01-31

Applicant: ST MICROELECTRONICS SA

Inventor： GARDES PASCAL ,  BLANCHARD STEPHANE ,  BOUFNICHEL MOHAMED

IPC: H01G4/30 ,  H01G4/38 ,  H01L27/06

Abstract: L'invention concerne un condensateur comprenant, sur un substrat (1) une succession de couches conductrices (19, 23, 27) séparées par des couches isolantes (21, 25) ; et des première et deuxième bornes (31, 33). Les couches conductrices (19, 23, 27) et isolantes (21, 25) s'étendent sur le substrat (1) et dans des portions évidées (17) du substrat (1), la première borne (31) étant reliée aux couches conductrices d'ordre pair (23) et la seconde borne (33) étant reliée aux couches conductrices d'ordre impair (19, 27).

公开(公告)号：FR2830670A1

公开(公告)日：2003-04-11

申请号：FR0113055

申请日：2001-10-10

Applicant: ST MICROELECTRONICS SA

Inventor： GARDES PASCAL ,  AURIEL GERARD

IPC: H01L27/04 ,  H01F17/00 ,  H01F41/04 ,  H01L21/02 ,  H01L21/71

Abstract: The monolithic circuit includes a substrate (11) on which an inductance is formed. This is achieved by depositing a conducting material on one wall of a spiral channel. The channel may be filled with insulating material. The monolithic circuit includes a substrate (11) on which an inductance is formed. On one surface of the substrate a channel (21) is formed, and this may be in the form of a spiral, extending between a central hole and an outer hole defining the outer end of the spiral. This channel may be formed by laser action. The surface of the channel and that of the end hole is then insulated. Insulation may be achieved in the process by thermal oxidation, whilst the channel itself may alternatively be cut by plasma etching. A conducting material is deposited on at least one wall of the channel, defining a conductive path between the two extreme holes. This conductive spiral forms the inductance. The channel may finally be filled with a further quantity of insulating material.

公开(公告)号：FR2830683A1

公开(公告)日：2003-04-11

申请号：FR0207383

申请日：2002-06-14

Applicant: ST MICROELECTRONICS SA

Inventor： GARDES PASCAL

IPC: H01L27/02 ,  H01F17/00 ,  H01F41/04 ,  H01L21/02 ,  H01L21/768 ,  H01L21/71 ,  H01F41/00

Abstract: The monolithic circuit includes a substrate (11) on which an inductance is formed. This is achieved by depositing a conducting material on one wall of a spiral channel. The channel may be filled with insulating material. The monolithic circuit includes a substrate (11) on which an inductance is formed. On one surface of the substrate a channel (21) is formed, and this may be in the form of a spiral, extending between a central hole and an outer hole defining the outer end of the spiral. This channel may be formed by laser action. The surface of the channel and that of the end hole is then insulated. Insulation may be achieved in the process by thermal oxidation, whilst the channel itself may alternatively be cut by plasma etching. A conducting material is deposited on at least one wall of the channel, defining a conductive path between the two extreme holes. This conductive spiral forms the inductance. The channel may finally be filled with a further quantity of insulating material.

公开(公告)号：DE60227898D1

公开(公告)日：2008-09-11

申请号：DE60227898

申请日：2002-10-09

Applicant: ST MICROELECTRONICS SA

Inventor： GARDES PASCAL

IPC: H01F41/04 ,  H01L27/02 ,  H01F17/00 ,  H01L21/02 ,  H01L21/768 ,  H01L23/64

Abstract: The monolithic circuit includes a substrate (11) on which an inductance is formed. This is achieved by depositing a conducting material on one wall of a spiral channel. The channel may be filled with insulating material. The monolithic circuit includes a substrate (11) on which an inductance is formed. On one surface of the substrate a channel (21) is formed, and this may be in the form of a spiral, extending between a central hole and an outer hole defining the outer end of the spiral. This channel may be formed by laser action. The surface of the channel and that of the end hole is then insulated. Insulation may be achieved in the process by thermal oxidation, whilst the channel itself may alternatively be cut by plasma etching. A conducting material is deposited on at least one wall of the channel, defining a conductive path between the two extreme holes. This conductive spiral forms the inductance. The channel may finally be filled with a further quantity of insulating material.

公开(公告)号：FR2832855A1

公开(公告)日：2003-05-30

申请号：FR0115307

申请日：2001-11-27

Applicant: ST MICROELECTRONICS SA

Inventor： GARDES PASCAL ,  AURIEL GERARD

IPC: H01F17/00 ,  H01F41/04 ,  H01L21/02 ,  H01L23/488 ,  H01L23/535

Abstract: The monolithic circuit includes a substrate (11) on which an inductance is formed. This is achieved by depositing a conducting material on one wall of a spiral channel. The channel may be filled with insulating material. The monolithic circuit includes a substrate (11) on which an inductance is formed. On one surface of the substrate a channel (21) is formed, and this may be in the form of a spiral, extending between a central hole and an outer hole defining the outer end of the spiral. This channel may be formed by laser action. The surface of the channel and that of the end hole is then insulated. Insulation may be achieved in the process by thermal oxidation, whilst the channel itself may alternatively be cut by plasma etching. A conducting material is deposited on at least one wall of the channel, defining a conductive path between the two extreme holes. This conductive spiral forms the inductance. The channel may finally be filled with a further quantity of insulating material.