公开(公告)号：FR2794277A1

公开(公告)日：2000-12-01

申请号：FR9906736

申请日：1999-05-25

Applicant: ST MICROELECTRONICS SA

Inventor： HANRIAT STEPHANE ,  BOROT BERTRAND

IPC: G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C17/12 ,  G11C11/40

Abstract: The read only memory structure has memory cells with columns of bits (BC) and lines of words (W) as well as a bit reference column (DBC). The reference bit column is made up of non programmed cells. The power to the voltage line (PUP) is activated (20) before activation of the word line. The length between the two activation processes are chose to minimise the variations of line levels with respect to the high voltage feed (Vdd).

公开(公告)号：FR2793591A1

公开(公告)日：2000-11-17

申请号：FR9906243

申请日：1999-05-12

Applicant: ST MICROELECTRONICS SA

Inventor： BOROT BERTRAND ,  HANRIAT STEPHANE

IPC: G11C17/12 ,  G11C11/40

Abstract: The read-only or dead memory comprises memory cells, each programmable cell constituted by a transistor (MN) connected between a bit line (BL) and the supply potential (Vdd), wherein the memory cells are arranged in ensembles of at least one column coupled to a reading amplifier (12) via a multiplexer (14). The programming of cells is inverted with respect to the desired programming only in specific ensembles, or the desired programming is carried out on a number of programming cells greater than the number of non-programming cells. The logic states delivered by the reading amplifiers associated to specific ensembles are inverted. Each reading amplifier (12) contains at least two stages (STG1, STG2) interconnected by two differential lines, which are inverted in the case of amplifiers associated with specific ensembles. Each ensemble can comprise a set of columns coupled to the respective reading amplifier (12) via a multiplexer (14). The reading amplifiers (12) have the role comparators, each with one input from a multiplexer (14) and the other input from the reference bit line (DBL), which is connected between a preloading transistor (MP) and the supply potential (Vdd), and corresponds to a column wherein all cells are programmed.

公开(公告)号：FR2793591B1

公开(公告)日：2004-01-02

申请号：FR9906243

申请日：1999-05-12

Applicant: ST MICROELECTRONICS SA

Inventor： BOROT BERTRAND ,  HANRIAT STEPHANE

IPC: G11C17/12 ,  G11C11/40

Abstract: A ROM including memory cells, the programmed cells being formed of a transistor connected between a bit line and a supply potential, the cells being organized in sets of at least one column coupled to one sense amplifier per set. The cell programming is inverted with respect to a desired programming only in specific sets where the desired programming would result in a number of programmed cells greater than the number of unprogrammed cells, the logic state provided by the sense amplifiers associated with the specific sets being inverted.

公开(公告)号：FR2794277B1

公开(公告)日：2001-08-10

申请号：FR9906736

申请日：1999-05-25

Applicant: ST MICROELECTRONICS SA

Inventor： HANRIAT STEPHANE ,  BOROT BERTRAND

IPC: G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C17/12 ,  G11C11/40

Abstract: A ROM including columns of memory cells connected by columns to respective bit lines; a reference bit line; charge transistors controllable by a common charge line and respectively connecting the bit lines and the reference bit line to a high supply potential. The reference bit line is associated with a column of unprogrammed cells, and the memory includes means for activating the charge line before activation of a word line, the duration between the activation of the charge line and the activation of the word line, and the features of the charge transistors, being chosen so that the level variation of the bit lines is low as compared to the level of the high supply potential.