公开(公告)号：FR2912842B1

公开(公告)日：2009-05-08

申请号：FR0753324

申请日：2007-02-19

Applicant: ST MICROELECTRONICS SA

Inventor： BOROT BERTRAND ,  BECHET EMMANUEL

IPC: H01L27/00 ,  G01R31/28 ,  H03K19/003

Abstract: An integrated circuit includes N configurable cells each including one functional input, one output, one propagation input and one output. The circuit includes a functional mode in which the N configurable cells are coupled by their functional input and their output to logic blocks with which they cooperate to form at least one logic circuit. The disclosed circuit also includes a test mode in which the N configurable cells are coupled by their propagation input and their output to the logic blocks and in which the output of the Nth configurable cell is coupled to a functional input of the first logic block to form an oscillator.

公开(公告)号：FR2794277A1

公开(公告)日：2000-12-01

申请号：FR9906736

申请日：1999-05-25

Applicant: ST MICROELECTRONICS SA

Inventor： HANRIAT STEPHANE ,  BOROT BERTRAND

IPC: G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C17/12 ,  G11C11/40

Abstract: The read only memory structure has memory cells with columns of bits (BC) and lines of words (W) as well as a bit reference column (DBC). The reference bit column is made up of non programmed cells. The power to the voltage line (PUP) is activated (20) before activation of the word line. The length between the two activation processes are chose to minimise the variations of line levels with respect to the high voltage feed (Vdd).

公开(公告)号：FR2793591A1

公开(公告)日：2000-11-17

申请号：FR9906243

申请日：1999-05-12

Applicant: ST MICROELECTRONICS SA

Inventor： BOROT BERTRAND ,  HANRIAT STEPHANE

IPC: G11C17/12 ,  G11C11/40

Abstract: The read-only or dead memory comprises memory cells, each programmable cell constituted by a transistor (MN) connected between a bit line (BL) and the supply potential (Vdd), wherein the memory cells are arranged in ensembles of at least one column coupled to a reading amplifier (12) via a multiplexer (14). The programming of cells is inverted with respect to the desired programming only in specific ensembles, or the desired programming is carried out on a number of programming cells greater than the number of non-programming cells. The logic states delivered by the reading amplifiers associated to specific ensembles are inverted. Each reading amplifier (12) contains at least two stages (STG1, STG2) interconnected by two differential lines, which are inverted in the case of amplifiers associated with specific ensembles. Each ensemble can comprise a set of columns coupled to the respective reading amplifier (12) via a multiplexer (14). The reading amplifiers (12) have the role comparators, each with one input from a multiplexer (14) and the other input from the reference bit line (DBL), which is connected between a preloading transistor (MP) and the supply potential (Vdd), and corresponds to a column wherein all cells are programmed.

公开(公告)号：FR2880982A1

公开(公告)日：2006-07-21

申请号：FR0500546

申请日：2005-01-19

Applicant: ST MICROELECTRONICS SA

Inventor： SCHOELLKOPF JEAN PIERRE ,  BOROT BERTRAND

IPC: G11C17/12 ,  H01L21/8246 ,  H01L29/423

Abstract: Mémoire en circuit intégré de type mémoire morte comprenant au moins une cellule-mémoire, chaque cellule-mémoire comportant un transistor de mémorisation réalisé dans un substrat semiconducteur (50) et présentant une source reliée à un potentiel de référence (GND), une grille reliée à une ligne de mot électriquement conductrice (WL), et un drain relié à une ligne de bit électriquement conductrice (BL) par l'intermédiaire d'une liaison (41 ; 51) optionnelle selon que la cellule-mémoire est affectée à la valeur 0 ou 1, le transistor de mémorisation de chaque cellule-mémoire présentant une grille (G4) formée sur le substrat (50), en forme de fenêtre dont le contour intérieur délimite dans le substrat une région centrale de drain (D4), et le contour extérieur délimite dans le substrat au moins une région de source (S4, S5).

公开(公告)号：FR2793591B1

公开(公告)日：2004-01-02

申请号：FR9906243

申请日：1999-05-12

Applicant: ST MICROELECTRONICS SA

Inventor： BOROT BERTRAND ,  HANRIAT STEPHANE

IPC: G11C17/12 ,  G11C11/40

Abstract: A ROM including memory cells, the programmed cells being formed of a transistor connected between a bit line and a supply potential, the cells being organized in sets of at least one column coupled to one sense amplifier per set. The cell programming is inverted with respect to a desired programming only in specific sets where the desired programming would result in a number of programmed cells greater than the number of unprogrammed cells, the logic state provided by the sense amplifiers associated with the specific sets being inverted.

公开(公告)号：FR2864337A1

公开(公告)日：2005-06-24

申请号：FR0351179

申请日：2003-12-23

Applicant: ST MICROELECTRONICS ROUSSET ,  ST MICROELECTRONICS SA ,  UNIV D AIX MARSEILLE I

Inventor： NEE DIDIER ,  FORLI LIONEL ,  BOROT BERTRAND ,  PORTAL JEAN MICHEL

IPC: G11C29/24 ,  G11C29/50 ,  H01L23/544 ,  H01L21/66

Abstract: The cell has two parallel branches provided between two input/output nodes (1, 2). One branch has an inverter (3) and another branch has two series inverters (4, 5). The inverter (5) is short-circuited by a switch (6) controllable by a control signal. The cell operates as static RAM cell to allow static test and as a ring oscillator to allow dynamic test, when the switch is closed and opened, respectively. Independent claims are also included for the following: (A) a test structure comprising a number of cells; and (B) a method to test an integrated circuit.

公开(公告)号：FR2794277B1

公开(公告)日：2001-08-10

申请号：FR9906736

申请日：1999-05-25

Applicant: ST MICROELECTRONICS SA

Inventor： HANRIAT STEPHANE ,  BOROT BERTRAND

IPC: G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C17/12 ,  G11C11/40

Abstract: A ROM including columns of memory cells connected by columns to respective bit lines; a reference bit line; charge transistors controllable by a common charge line and respectively connecting the bit lines and the reference bit line to a high supply potential. The reference bit line is associated with a column of unprogrammed cells, and the memory includes means for activating the charge line before activation of a word line, the duration between the activation of the charge line and the activation of the word line, and the features of the charge transistors, being chosen so that the level variation of the bit lines is low as compared to the level of the high supply potential.

公开(公告)号：FR2901362B1

公开(公告)日：2011-03-11

申请号：FR0604475

申请日：2006-05-19

Applicant: ST MICROELECTRONICS SA

Inventor： TURGIS DAVID ,  BOROT BERTRAND

IPC: G01R31/3187 ,  G11C29/00

公开(公告)号：FR2912842A1

公开(公告)日：2008-08-22

申请号：FR0753324

申请日：2007-02-19

Applicant: ST MICROELECTRONICS SA

Inventor： BOROT BERTRAND ,  BECHET EMMANUEL

IPC: H01L27/00 ,  G01R31/28 ,  H03K19/003

Abstract: L'invention concerne un circuit intégré comprenant N cellules configurables (CC1, ..., CCN) comprenant chacune une entrée fonctionnelle (D), une entrée de propagation (CK ou S) et une sortie (Q), le circuit comprenant un mode fonctionnel dans lequel les N cellules configurables sont reliées par leur entrée fonctionnelle et leur sortie à des blocs logiques (BL1, ..., BLN) avec lesquels elles coopèrent pour former au moins un circuit logique.Le circuit selon l'invention est caractérisé en ce qu'il comprend également un mode de test dans lequel les N cellules configurables sont reliées par leur entrée de propagation et leur sortie aux blocs logiques et dans lequel la sortie de la N-ième cellule configurable (CCN) est reliée à une entrée fonctionnelle du premier bloc logique (BL1) pour former un oscillateur.Application au test de performances et de consommation des circuits intégrés.

公开(公告)号：FR2901362A1

公开(公告)日：2007-11-23

申请号：FR0604475

申请日：2006-05-19

Applicant: ST MICROELECTRONICS SA

Inventor： TURGIS DAVID ,  BOROT BERTRAND

IPC: G01R31/3187 ,  G11C29/00

Abstract: Un circuit et procédé de qualification ou de caractérisation d'une mémoire (600) intégrée dans un circuit semi-conducteur et comportant un circuit d'adressage (ADD), un circuit d'horloge (CK) et un circuit de lecture (Q). Le circuit comporte :- des moyens d'initialisation (RAZ) de la mémoire venant charger au moins deux points mémoires avec deux valeurs complémentaires, lesdits points mémoires étant respectivement adressables via une première et une seconde adresses ;- une boucle d'oscillation comportant un circuit logique permettant de générer alternativement lesdites première et seconde adresses à partir des données lues en mémoire de manière à provoquer une alternance d'opérations de lecture entre lesdits premier et second point mémoires provoquant ainsi un phénomène oscillatoire mesurable en interne ou en externe et dont la fréquence dépend des paramètres internes de ladite mémoire.