公开(公告)号：JP2000124132A

公开(公告)日：2000-04-28

申请号：JP27435199

申请日：1999-09-28

Applicant: ST MICROELECTRONICS SA

Inventor： DUTARTRE DIDIER ,  JERIER PATRICK

IPC: H01L21/302 ,  H01L21/205 ,  H01L21/22 ,  H01L21/3065 ,  H01L21/203

Abstract: PROBLEM TO BE SOLVED: To avoid self-doping by etching a Si substrate by a specified thickness with a silicon chloride compound gas introduced before depositing in the vapor phase epitaxial deposition on the Si substrate having high-concentration dopant regions. SOLUTION: In the vapor phase epitaxial deposition on a Si substrate 1 having dopant regions 6, 7 containing boron at a high concentration, the initial annealing is selectively made and the epitaxial deposition is made for a given time to obtain an epitaxial layer 5 having a desired usual thickness. Before the epitaxial deposition, a silicon chloride compound gas is introduced to etch the Si substrate 1 by a thickness of about 100 nm or less to thereby remove a self-doped layer of boron to the epitaxial layer 5. Thus the self-doping of boron to the epitaxial layer 5 is reduced.

公开(公告)号：JP2000040668A

公开(公告)日：2000-02-08

申请号：JP13872099

申请日：1999-05-19

Applicant: ST MICROELECTRONICS SA

Inventor： DUTARTRE DIDIER ,  JERIER PATRICK

IPC: H01L21/225 ,  H01L21/205 ,  H01L21/22 ,  H01L21/74 ,  H01L21/8249 ,  H01L27/06

Abstract: PROBLEM TO BE SOLVED: To limit doping of a growth layer without increasing boron self-doping, by a method wherein an epitaxially grown silicon layer is deposited on a single crystalline silicon substrate that comprises zones of high concentrations of arsenic or phosphorus restraining it from being self-doped with arsenic or phosphorus. SOLUTION: Germanium compound as GeH4 gas is added in the gas phase during an annealing time from a point of time t5 to a point of time t6, a deposition process is stopped from a point, of time t6 to a point, of time t2, and a time t5 to t6 for adding a compound GeH4 is selectively set at ten seconds to tens of seconds. After Ge is deposited, hydrogen is purged for a time (tens of seconds) t6 to t2 at a temperature T1. An epitaxially grown silicon layer is self-doped for a time t3 to t4 and a block doped with arsenic and a non-doped block are formed at this deposition of Ge. Ge is deposited on a second test wafer of an epitaxially grown non-doped silicon layer for a time t5 to t6, and hydrogen is adsorbed and/or desorbed.

公开(公告)号：FR2784501A1

公开(公告)日：2000-04-14

申请号：FR9812755

申请日：1998-10-07

Applicant: ST MICROELECTRONICS SA

Inventor： DUTARTRE DIDIER ,  JERIER PATRICK

IPC: H01L21/302 ,  H01L21/205 ,  H01L21/22 ,  H01L21/3065

Abstract: Forming a deposit of silicon by vapor phase epitaxy on silicon substrate having zones containing high concentration dopants including boron, and avoiding self-doping of the epitaxial layer with boron, comprises introducing chlorinated gas to etch the substrate within a thickness below 100 nm, before forming the epitaxial layer while the substrate is held at high temperature.

公开(公告)号：DE69916699D1

公开(公告)日：2004-06-03

申请号：DE69916699

申请日：1999-05-18

Applicant: ST MICROELECTRONICS SA

Inventor： DUTARTRE DIDIER ,  JERIER PATRICK

IPC: H01L21/225 ,  H01L21/205 ,  H01L21/22 ,  H01L21/74 ,  H01L21/8249 ,  H01L27/06

公开(公告)号：DE69916699T2

公开(公告)日：2005-04-07

申请号：DE69916699

申请日：1999-05-18

Applicant: ST MICROELECTRONICS SA

Inventor： DUTARTRE DIDIER ,  JERIER PATRICK

IPC: H01L21/225 ,  H01L21/205 ,  H01L21/22 ,  H01L21/74 ,  H01L21/8249 ,  H01L27/06

公开(公告)号：DE69821560T2

公开(公告)日：2005-01-05

申请号：DE69821560

申请日：1998-07-28

Applicant: ST MICROELECTRONICS SA

Inventor： DUTARTRE DIDIER ,  JERIER PATRICK

IPC: C30B29/06 ,  C23C16/24 ,  C30B25/02 ,  C30B25/20 ,  H01L21/205

Abstract: In a process for gas phase epitaxial deposition of silicon on a silicon substrate having doped zones of high arsenic concentration, self-doping of the epitaxial layer with arsenic is avoided by (a) carrying out a first thin epitaxial deposition (t5-t6) and subsequent anneal (t6-t3) under conditions and for a time such that the arsenic diffusion length is much less than the deposited layer thickness; and (b) carrying out a second epitaxial deposition (t3-t4) to achieve the desired layer thickness. Preferably, step (a) is carried out at 1100 degrees C for a time to achieve 40-60 nm thickness and step (b) is carried out at 1050 degrees C.

公开(公告)号：DE69821560D1

公开(公告)日：2004-03-18

申请号：DE69821560

申请日：1998-07-28

Applicant: ST MICROELECTRONICS SA ,  FRANCE TELECOM

Inventor： DUTARTRE DIDIER ,  JERIER PATRICK

IPC: C30B29/06 ,  C23C16/24 ,  C30B25/02 ,  C30B25/20 ,  H01L21/205

Abstract: In a process for gas phase epitaxial deposition of silicon on a silicon substrate having doped zones of high arsenic concentration, self-doping of the epitaxial layer with arsenic is avoided by (a) carrying out a first thin epitaxial deposition (t5-t6) and subsequent anneal (t6-t3) under conditions and for a time such that the arsenic diffusion length is much less than the deposited layer thickness; and (b) carrying out a second epitaxial deposition (t3-t4) to achieve the desired layer thickness. Preferably, step (a) is carried out at 1100 degrees C for a time to achieve 40-60 nm thickness and step (b) is carried out at 1050 degrees C.

公开(公告)号：FR2784501B1

公开(公告)日：2003-01-31

申请号：FR9812755

申请日：1998-10-07

Applicant: ST MICROELECTRONICS SA

Inventor： DUTARTRE DIDIER ,  JERIER PATRICK

IPC: H01L21/302 ,  H01L21/205 ,  H01L21/22 ,  H01L21/3065

Abstract: Forming a deposit of silicon by vapor phase epitaxy on silicon substrate having zones containing high concentration dopants including boron, and avoiding self-doping of the epitaxial layer with boron, comprises introducing chlorinated gas to etch the substrate within a thickness below 100 nm, before forming the epitaxial layer while the substrate is held at high temperature.