公开(公告)号：FR2854747A1

公开(公告)日：2004-11-12

申请号：FR0305648

申请日：2003-05-09

Applicant: ST MICROELECTRONICS SA

Inventor： URARD PASCAL ,  PAUMIER LAURENT ,  LANTREIBECQ ETIENNE

IPC: H03M13/41 ,  H03M13/23

公开(公告)号：FR2857178A1

公开(公告)日：2005-01-07

申请号：FR0308238

申请日：2003-07-04

Applicant: ST MICROELECTRONICS SA

Inventor： URARD PASCAL ,  PAUMIER LAURENT ,  LANTREIBECQ ETIENNE

IPC: H03M13/27

Abstract: The interleaver has two random access memories (RAMs) (10, 11) to store data, and an addressing device (100) connected to respective address inputs of the RAMs. The device is arranged to transmit, at each instant of a clock, a reading instruction to one of the RAMs and a writing instruction to the other RAM, such that data is written in/read from each RAM, at each instant. An independent claim is also included for a digital signal decoding device having an interleaver and a decoder.

公开(公告)号：FR2857178B1

公开(公告)日：2005-09-30

申请号：FR0308238

申请日：2003-07-04

Applicant: ST MICROELECTRONICS SA

Inventor： URARD PASCAL ,  PAUMIER LAURENT ,  LANTREIBECQ ETIENNE

IPC: H03M13/27

Abstract: The interleaver has two random access memories (RAMs) (10, 11) to store data, and an addressing device (100) connected to respective address inputs of the RAMs. The device is arranged to transmit, at each instant of a clock, a reading instruction to one of the RAMs and a writing instruction to the other RAM, such that data is written in/read from each RAM, at each instant. An independent claim is also included for a digital signal decoding device having an interleaver and a decoder.