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    1.
    发明专利
    未知

    公开(公告)号：FR2868627B1

    公开(公告)日：2006-06-16

    申请号：FR0403500

    申请日：2004-04-02

    Applicant: ST MICROELECTRONICS SA

    Inventor： LENZ KUNO

    IPC: H03H1/00 ,  H01C13/02 ,  H03G1/00 ,  H03G3/00 ,  H03H7/06

    Abstract: An integrated circuit includes a resistive circuit with reduced mismatch that includes a primary resistive network with several main resistances (Rp) each having the same theoretical main value. It also includes an auxiliary resistance (Rau) having an auxiliary theoretical resistive value equal to the product or to the quotient of the theoretical main resistive value by √{square root over (2. All these resistances are connected together so as to attribute a theoretical overall resistive value to the primary resistive network equal to the theoretical auxiliary resistive value.

    Differential amplifier with low level of noise, comprises two amplifiers equipped with output stages containing capacitors and a follower stage connected to the capacitors
    4.
    发明专利
    Differential amplifier with low level of noise, comprises two amplifiers equipped with output stages containing capacitors and a follower stage connected to the capacitors 未知

    公开(公告)号：FR2833430A1

    公开(公告)日：2003-06-13

    申请号：FR0116052

    申请日：2001-12-12

    Applicant: ST MICROELECTRONICS SA

    Inventor： RENOUS CLAUDE ,  LENZ KUNO

    IPC: H03F1/08 ,  H03F1/26

    Abstract: The structure of the differential amplifier circuit incorporating a stabilization circuit comprises two amplifiers (OA1,OA2) equipped with output stages containing the Miller capacitors (Cm) and compensating capacitors (Cmc), and a follower stage containing an amplifier (OA3) receiving the common-mode potential (VCM) and whose output is connected to the compensating capacitors (Cmc). The input of the follower stage is connected to the midpoint of a resistor bridge comprising four resistors, which is connected between the output (OUTP) of the first amlifiers (OA1) and the output (OUTN) of the second amplifier (OA2). The positive inputs of the amplifiers (OA1,OA2) are connected to the circuit inputs (INP,INN), respectively, by the intermediary of decoupling capacitors (C). The negative input of each of two amplifiers (OA1,OA2) is connected to a midpoint of two resistors. The resistor (R) fixes the input impedance of the amplifier circuit. The follower stage is implemented by use of a transistor of type MOS in series with a current source. In the second embodiment, the amplifier circuit is of a variable-gain amplifier which comprises two sets of compensating capacitors, some connectable by switches. In the third embodiment, the amplifier circuit comprises two amplifiers and two compensation circuits with capacitors, and has significantly lower supply current.

    Mixer comprising biasing circuit with current-mirror connected to current source in input intermediate-frequency stage, for use in telecommunications
    5.
    发明专利
    Mixer comprising biasing circuit with current-mirror connected to current source in input intermediate-frequency stage, for use in telecommunications 未知

    公开(公告)号：FR2814607A1

    公开(公告)日：2002-03-29

    申请号：FR0012221

    申请日：2000-09-26

    Applicant: ST MICROELECTRONICS SA

    Inventor： GRASSET JEAN CHARLES ,  CATHELIN PHILIPPE ,  LENZ KUNO

    IPC: H03D7/14 ,  H03D7/00

    Abstract: The mixer comprises an input intermediate-frequency (IF) stage (10), and a stage for the frequency shifting and output (20) delivering the radio-frequency differential-output signals (RFN,RFP). The biasing network (35) of the output stage comprises a constant current source (10) connected in parallel with a transistor (P3) of a current-mirror (M), whose other transistor (P2) is connected to a transisstor (P1) of a current source (11) of the input stage, and a resistor (R0) connected in series with two diodes (D1,D2) between the biasing node (14) and the ground. The transistors (P1,P2,P3) are of p-MOS type. The input stage (10) is with variable stationary-state current. The constant current source (10) is of bandgap type to ensure a constant voltage on the resistor (R0). The supply voltage (Vdd) is relatively low, e.g. 2.7 V. The input stage (10) comprises, as in prior device, a bipolar transistor (T1), a resistor (RE) connected between the emitter and the ground, a capacitor (CF) for the input of intermediate-frequency signal (IF), a current source (11) with a transistor (P1), a comparator (12), and a variable-voltage source (13). The collector of transistor (T1) delivers the intermediate-frequency signal (IF') with adjusted stationary-state level to the output stage. The output stage comprises a differential pair of bipolar transistors (TN,TP), capacitors (CN,CP) for the input of local-oscillator signals (LON,LOP) phase-shifted by 180 deg. and resistors (RN,RP) connecting the bases of transistors to the biasing node.

    CIRCUIT INTEGRE AVEC RESEAU RESISTIF A DESAPPARIEMENT REDUIT
    6.
    发明专利
    CIRCUIT INTEGRE AVEC RESEAU RESISTIF A DESAPPARIEMENT REDUIT 未知

    公开(公告)号：FR2868627A1

    公开(公告)日：2005-10-07

    申请号：FR0403500

    申请日：2004-04-02

    Applicant: ST MICROELECTRONICS SA

    Inventor： LENZ KUNO

    IPC: H01C13/02 ,  H03G1/00 ,  H03G3/00 ,  H03H1/00 ,  H03H7/06

    Abstract: Un circuit intégré comprend un circuit résistif à désappariement réduit comportant un réseau résistif primaire avec plusieurs résistances principales (Rp) ayant chacune la même valeur principale théorique. Il comprend en outre une résistance auxiliaire (Rau) ayant une valeur résistive théorique auxiliaire égale au produit ou au quotient de ladite valeur résistive principale théorique par √2. Toutes ces résistances sont mutuellement connectées de façon à conférer au réseau résistif primaire une valeur résistive globale théorique égale à ladite valeur résistive auxiliaire théorique.

    9.
    发明专利
    未知

    公开(公告)号：FR2814607B1

    公开(公告)日：2003-02-07

    申请号：FR0012221

    申请日：2000-09-26

    Applicant: ST MICROELECTRONICS SA

    Inventor： GRASSET JEAN CHARLES ,  CATHELIN PHILIPPE ,  LENZ KUNO

    IPC: H03D7/14 ,  H03D7/00

    Abstract: A mixer including a stage for inputting a voltage signal to be shifted and a shift and output stage for providing frequency-shifted signals, a biasing network of the output stage including, between a high supply and a biasing node, a constant current source in parallel with an output element of a current mirror, an input element of which receives a bias order from the input stage.

    CIRCUIT DE PILOTAGE DE BUS
    10.
    发明专利
    CIRCUIT DE PILOTAGE DE BUS 未知

    公开(公告)号：FR2879321A1

    公开(公告)日：2006-06-16

    申请号：FR0413139

    申请日：2004-12-09

    Applicant: ST MICROELECTRONICS SA

    Inventor： LENZ KUNO

    IPC: G06F13/40 ,  H03K19/0185

    Abstract: L'invention apporte une solution pour permettre d'accroître la vitesse de commutation d'un circuit de pilotage de bus 100 comportant une paire de transistors 101 et 102 commandé par une paire de circuits de commande 103 et 104. Des circuits de pompage 110 et 120 sont placés entre les électrodes de commande des transistors 101 et 102 pour accélérer la conduction de l'un des transistors 101 ou 102 dès que l'autre est dans un état bloqué. Une interface de sortie pour un bus différentiel est réalisée à l'aide de deux circuits de pilotage de bus, les signaux de commande de l'un desdits circuits étant inversés par rapport à l'autre desdits circuits.

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