公开(公告)号：DE69700156D1

公开(公告)日：1999-04-29

申请号：DE69700156

申请日：1997-09-23

Applicant: ST MICROELECTRONICS SA

Inventor： LOPEZ JOAQUIM RAMON ,  NAURA DAVID

IPC: G11C7/24 ,  G11C16/22 ,  G11C16/06 ,  G11C7/00

Abstract: The memory includes an array of cells obtained on a silicon chip with four input terminals receiving chip selection signals, data and addresses. A clock signal (SK) is applied to the third terminal while the last terminal receives a signal (8B) indicating the operating mode of the memory i.e. 8 or 16 bits. A delay register is connected to the second terminal of the memory and the clock which generates the signal SK. A signal forming circuit (5) interfaces between the clock and the memory input terminal. A counter (7) and a validation circuit (8) are connected to the clock. A control circuit (10) disables or enables writing to the memory function of the validation signal received.

公开(公告)号：DE69700156T2

公开(公告)日：1999-07-22

申请号：DE69700156

申请日：1997-09-23

Applicant: ST MICROELECTRONICS SA

Inventor： LOPEZ JOAQUIM RAMON ,  NAURA DAVID

IPC: G11C7/24 ,  G11C16/22 ,  G11C16/06 ,  G11C7/00

Abstract: The memory includes an array of cells obtained on a silicon chip with four input terminals receiving chip selection signals, data and addresses. A clock signal (SK) is applied to the third terminal while the last terminal receives a signal (8B) indicating the operating mode of the memory i.e. 8 or 16 bits. A delay register is connected to the second terminal of the memory and the clock which generates the signal SK. A signal forming circuit (5) interfaces between the clock and the memory input terminal. A counter (7) and a validation circuit (8) are connected to the clock. A control circuit (10) disables or enables writing to the memory function of the validation signal received.