公开(公告)号：JP2001155492A

公开(公告)日：2001-06-08

申请号：JP2000299140

申请日：2000-09-29

Applicant: ST MICROELECTRONICS SA

Inventor： ZINK SEBASTIEN ,  BERTRAND BERTRAND ,  NAURA DAVID

IPC: G11C16/06 ,  G11C7/10 ,  G11C16/08 ,  G11C16/10

Abstract: PROBLEM TO BE SOLVED: To reduce occupied area of a shift register of an EEPROM integrated circuit serial access type memory. SOLUTION: This memory is provided with a data input DI, a data output D0, a memory plane MM constituted of memory words, a set LAT of a column register in which one register is combined with at least one memory word, a first means operated for loading directly binary data of a binary word received at a data input Di to each storage/switching latches HV0-HV7 of a column register R1 combined with memory words M0-M7 during writein operation of a binary word for the prescribed memory words M0-M7, and/or a second means operated for reading out continuously binary data stored in a memory cell of a memory word transmitting each read-out binary data to the data output D0 of a memory with a direct serial form during read-out operation of binary words in memory words.

公开(公告)号：JP2001118394A

公开(公告)日：2001-04-27

申请号：JP2000281033

申请日：2000-09-14

Applicant: ST MICROELECTRONICS SA

Inventor： NAURA DAVID ,  ZINK SEBASTIEN ,  BERTRAND BERTRAND

IPC: G11C16/02 ,  G11C16/06 ,  G11C16/10

Abstract: PROBLEM TO BE SOLVED: To decrease the number of required high voltage latch without lengthening excessively a page mode access time. SOLUTION: In a page mode write-in method of a non-volatile memory being electrically erasable and programmable in an integrated circuit, a written page corresponds to a column of a memory array. This method comprises write-in of information elements for selecting a page written in a storage latch combined with columns of a non-volatile memory array, an initial stage including writing each data written in a page in a temporary storage device, and a write-in stage selecting a row of a non-volatile memory array conforming to contents of the temporary storage device. The page mode write-in means is provided with one latch per one column of a non-volatile memory array, and a control logic circuit outputting a row selecting signal in accordance with contents of the temporary storage device at a stage at which a column of the non-volatile memory array is written, in order to storing page selection information elements.

公开(公告)号：WO2007023213A3

公开(公告)日：2007-04-12

申请号：PCT/FR2006001768

申请日：2006-07-19

Applicant: ST MICROELECTRONICS SA ,  MOREAUX CHRISTOPHE ,  KARI AHMED ,  NAURA DAVID ,  RIZZO PIERRE

Inventor： MOREAUX CHRISTOPHE ,  KARI AHMED ,  NAURA DAVID ,  RIZZO PIERRE

IPC: G06F12/02

CPC classification number: G06F12/0292

Abstract: The invention relates to a method of configuring a memory space (MEM), comprising the following steps consisting in: reading a configuration datum (SZ3) in the memory space (MEM) and dividing at least part of the memory space into memory areas (Z1-Z4) as a function of the configuration datum read; and assigning each memory area with an access number (NBK) that is used to access a datum location in the memory area, together with a logical address of the location in the memory area. The invention is suitable for RFID chips.

Abstract translation: 本发明涉及一种配置存储空间（MEM）的方法，包括以下步骤：读取存储空间（MEM）中的配置数据（SZ3），并将至少部分存储空间划分为存储区域（Z1 -Z4）作为配置数据读取的函数; 以及为每个存储区域分配用于访问存储区域中的数据位置的访问号码（NBK）以及存储区域中的位置的逻辑地址。 本发明适用于RFID芯片。

公开(公告)号：DE602006000534T2

公开(公告)日：2009-02-19

申请号：DE602006000534

申请日：2006-08-28

Applicant: ST MICROELECTRONICS SA

Inventor： NAURA DAVID ,  KARI AHMED ,  MOREAUX CHRISTOPHE ,  RIZZO PIERRE

IPC: G11C16/22

Abstract: The circuit has a memory (MEM1) containing transaction data, with electrically erasable and programmable memory cells (C i, j) arranged in horizontal and vertical lines, and linked to word lines (WL i) and bit lines (BL j). A control unit (CTU) executes commands for reading or writing in the memory. The CTU is blocked when reference memory cells of one of the groups contain bits of equal value and if the value is different from a value expected for the one of the groups. The CTU controls a voltage generator (VGEN) which supplies a read voltage (Vread) and an erase-programming voltage (Vpp). An independent claim is also included for a method for protecting an integrated circuit against a global data erasure.

公开(公告)号：DE602006000534D1

公开(公告)日：2008-03-27

申请号：DE602006000534

申请日：2006-08-28

Applicant: ST MICROELECTRONICS SA

Inventor： NAURA DAVID ,  KARI AHMED ,  MOREAUX CHRISTOPHE ,  RIZZO PIERRE

IPC: G11C16/22

Abstract: The circuit has a memory (MEM1) containing transaction data, with electrically erasable and programmable memory cells (C i, j) arranged in horizontal and vertical lines, and linked to word lines (WL i) and bit lines (BL j). A control unit (CTU) executes commands for reading or writing in the memory. The CTU is blocked when reference memory cells of one of the groups contain bits of equal value and if the value is different from a value expected for the one of the groups. The CTU controls a voltage generator (VGEN) which supplies a read voltage (Vread) and an erase-programming voltage (Vpp). An independent claim is also included for a method for protecting an integrated circuit against a global data erasure.

公开(公告)号：FR2894710A1

公开(公告)日：2007-06-15

申请号：FR0512631

申请日：2005-12-14

Applicant: ST MICROELECTRONICS SA

Inventor： KARI AHMED ,  MOREAUX CHRISTOPHE ,  NAURA DAVID ,  RIZZO PIERRE

IPC: G11C29/52 ,  G11C7/24

Abstract: L'invention concerne un procédé d'exécution d'une commande d'écriture d'un mot binaire dans une mémoire programmable, comprenant des étapes d'écriture de chacun des bits (RB) dans un état programmé d'un mot binaire à écrire (D) dans une cellule mémoire correspondante de la mémoire, de lecture de chaque bit (MB) du mot écrit dans la mémoire (MEM) correspondant à un bit (RB) à l'état programmé du mot à écrire, de comparaison de chaque bit (RB) à l'état programmé du mot à écrire à un bit correspondant (MB) lu dans la mémoire, et de génération d'un signal d'erreur (ER) si au moins un bit du mot à écrire à l'état programmé est différent du bit correspondant lu. Application de l'invention notamment aux circuits intégrés pour carte à puce.

公开(公告)号：DE69700156D1

公开(公告)日：1999-04-29

申请号：DE69700156

申请日：1997-09-23

Applicant: ST MICROELECTRONICS SA

Inventor： LOPEZ JOAQUIM RAMON ,  NAURA DAVID

IPC: G11C7/24 ,  G11C16/22 ,  G11C16/06 ,  G11C7/00

Abstract: The memory includes an array of cells obtained on a silicon chip with four input terminals receiving chip selection signals, data and addresses. A clock signal (SK) is applied to the third terminal while the last terminal receives a signal (8B) indicating the operating mode of the memory i.e. 8 or 16 bits. A delay register is connected to the second terminal of the memory and the clock which generates the signal SK. A signal forming circuit (5) interfaces between the clock and the memory input terminal. A counter (7) and a validation circuit (8) are connected to the clock. A control circuit (10) disables or enables writing to the memory function of the validation signal received.

公开(公告)号：DE60226800D1

公开(公告)日：2008-07-10

申请号：DE60226800

申请日：2002-03-05

Applicant: ST MICROELECTRONICS SA

Inventor： NAURA DAVID ,  BERTRAND BERTRAND ,  CHEHADI MOHAMAD

IPC: G11C16/12

Abstract: A circuit produces a voltage for the erasure or programming of a memory cell. The circuit includes a capacitor, and a discharge circuit connected to a first terminal of the capacitor. The discharge circuit includes a first transistor, a drain of which is connected to the first terminal of the capacitor. The first transistor activates the discharge circuit when a discharge signal is received by a gate of the first transistor. The discharge circuit includes a slow discharge arm and a fast discharge arm parallel-connected to the source of the first transistor. The discharge circuit produces a low discharge current or a high discharge current for discharging the capacitor as a function of an operating mode selection signal.

公开(公告)号：DE602005002223D1

公开(公告)日：2007-10-11

申请号：DE602005002223

申请日：2005-10-27

Applicant: ST MICROELECTRONICS SA

Inventor： KARI AHMED ,  NAURA DAVID

IPC: H04L25/49 ,  H04L7/02

Abstract: The method involves generating a edge detection signal (FD) from an encoded data signal (CD) and sampling four pulses of the edge detection signal in a manner to obtain a decoded binary data signal (BD). A binary clock signal (CLK) is generated from the detection signal, where the clock signal is synchronous with the encoded data signal, for changing a logic state of the pulses of the detection signal. An independent claim is also included for a device for decoding a binary encoded data signal and generating a clock signal synchronous with the encoded data signal.

公开(公告)号：FR2891653A1

公开(公告)日：2007-04-06

申请号：FR0510158

申请日：2005-10-05

Applicant: ST MICROELECTRONICS SA

Inventor： KARI AHMED ,  MOREAUX CHRISTOPHE ,  NAURA DAVID ,  RIZZO PIERRE

IPC: G11C16/10 ,  G06K7/08 ,  G06K19/073

Abstract: L'invention concerne un procédé d'écriture par bloc dans une mémoire non volatile programmable électriquement, un bloc à écrire dans la mémoire comprenant au moins un mot. Selon l'invention, le procédé comprend des étapes de détermination d'une durée d'écriture d'un mot en divisant une durée fixée d'écriture d'un bloc par le nombre de mots du bloc à écrire, et de commande de la mémoire pour écrire successivement chaque mot (D) dans la mémoire pendant la durée d'écriture.