公开(公告)号：FR2821450A1

公开(公告)日：2002-08-30

申请号：FR0102645

申请日：2001-02-27

Applicant: ST MICROELECTRONICS SA

Inventor： COFLER ANDREW ,  MERLANDE ANNE ,  FERROUSSAT SEBASTIEN

IPC: G06F9/32 ,  G06F9/38 ,  G06F15/00

Abstract: Method for managing branching instructions at the heart of a processor (CR), which comprises a number of processing units (AU, DU) and a central unit (CU). The central unit assigns instructions to corresponding processing units. A clocking circuit times the processor core (CR), such that each time a branching instruction is received by the central unit it is treated in the same cycle. An Independent claim is made for a processor in which the central unit itself comprising a branching unit, i.e. it is on chip rather than being pipelined as currently. Problems arising with address registers due to this arrangement are solved by checking the validity of the pointer register concerned at the beginning of each cycle and use of a buffer register if necessary.

公开(公告)号：FR2821450B1

公开(公告)日：2004-07-09

申请号：FR0102645

申请日：2001-02-27

Applicant: ST MICROELECTRONICS SA

Inventor： COFLER ANDREW ,  MERLANDE ANNE ,  FERROUSSAT SEBASTIEN

IPC: G06F9/32 ,  G06F9/38 ,  G06F15/00

Abstract: Method for managing branching instructions at the heart of a processor (CR), which comprises a number of processing units (AU, DU) and a central unit (CU). The central unit assigns instructions to corresponding processing units. A clocking circuit times the processor core (CR), such that each time a branching instruction is received by the central unit it is treated in the same cycle. An Independent claim is made for a processor in which the central unit itself comprising a branching unit, i.e. it is on chip rather than being pipelined as currently. Problems arising with address registers due to this arrangement are solved by checking the validity of the pointer register concerned at the beginning of each cycle and use of a buffer register if necessary.